IPD50N04S4L08ATMA1

IPD50N04S4L-08
OptiMOS
®
-T2 Power-Transistor
Features
• N-channel - Enhancement mode
• AEC qualified
• MSL1 up to 260°C peak reflow
• 175°C operating temperature
• Green Product (RoHS compliant)
• 100% Avalanche tested
Maximum ratings, at T
j
=25 °C, unless otherwise specified
Parameter Symbol Conditions Unit
Continuous drain current
1)
I
D
T
C
=25°C, V
GS
=10V
50 A
T
C
=100°C, V
GS
=10V
2)
49
Pulsed drain current
2)
I
D,pulse
T
C
=25°C
200
Avalanche energy, single pulse
2)
E
AS
I
D
=25A
55 mJ
Avalanche current, single pulse
I
AS
-
50 A
Gate source voltage
V
GS
- +20/-16 V
Power dissipation
P
tot
T
C
=25°C
46 W
Operating and storage temperature
T
j
, T
stg
- -55 ... +175 °C
IEC climatic category; DIN IEC 68-1 - - 55/175/56
Value
V
DS
40 V
R
DS(on),max
7.3
m
I
D
50 A
Product Summary
PG-TO252-3-313
Type Package Marking
IPD50N04S4-08 PG-TO252-3-313 4N04L08
Rev. 1.0 page 1 2010-04-06
IPD50N04S4L-08
Parameter Symbol Conditions Unit
min. typ. max.
Thermal characteristics
2)
Thermal resistance, junction - case
R
thJC
- - - 3.3 K/W
Thermal resistance, junction -
ambient, leaded
R
thJA
---62
SMD version, device on PCB
R
thJA
minimal footprint - - 62
6 cm
2
cooling area
3)
--40
Electrical characteristics, at T
j
=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage
V
(BR)DSS
V
GS
=0V, I
D
= 1mA
40 - - V
Gate threshold voltage
V
GS(th)
V
DS
=V
GS
, I
D
=17µA
1.2 1.7 2.2
Zero gate voltage drain current
I
DSS
V
DS
=40V, V
GS
=0V,
T
j
=25°C
- 0.01 1 µA
V
DS
=18V, V
GS
=0V,
T
j
=85°C
2)
-120
Gate-source leakage current
I
GSS
V
GS
=20V, V
DS
=0V
- - 100 nA
Drain-source on-state resistance
R
DS(on)
V
GS
=4.5V, I
D
=25A
- 8.8 10.5
m
V
GS
=10 V, I
D
=50 A
- 6.2 7.3
Values
Rev. 1.0 page 2 2010-04-06
IPD50N04S4L-08
Parameter Symbol Conditions Unit
min. typ. max.
D
y
namic characteristics
2)
Input capacitance
C
iss
- 1800 2340 pF
Output capacitance
C
oss
- 350 455
Reverse transfer capacitance
C
rss
-1535
Turn-on delay time
t
d(on)
-4-ns
Rise time
t
r
-8-
Turn-off delay time
t
d(off)
-11-
Fall time
t
f
-18-
Gate Char
g
e Characteristics
2)
Gate to source charge
Q
gs
- 5.8 7.5 nC
Gate to drain charge
Q
gd
- 2.6 6.0
Gate charge total
Q
g
-2330
Gate plateau voltage
V
plateau
- 3.2 - V
Reverse Diode
Diode continous forward current
2)
I
S
- - 50 A
Diode pulse current
2)
I
S,pulse
- - 200
Diode forward voltage
V
SD
V
GS
=0V, I
F
=50A,
T
j
=25°C
- 0.9 1.3 V
Reverse recovery time
2)
t
rr
V
R
=20V, I
F
=50A,
di
F
/dt =100A/µs
-34-ns
Reverse recovery charge
2)
Q
rr
-27-nC
2)
Defined by design. Not subject to production test.
3)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm
2
(one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
1)
Current is limited by bondwire; with an R
thJC
= 3.3K/W the chip is able to carry 56A at 25°C. For detailed information
see Application Note ANPS071E
T
C
=25°C
Values
V
GS
=0 V, V
DS
=25 V,
f =1 MHz
V
DD
=20V, V
GS
=10V,
I
D
=50A, R
G
=3.5
V
DD
=32V, I
D
=50A,
V
GS
=0 to 10V
Rev. 1.0 page 3 2010-04-06

IPD50N04S4L08ATMA1

Mfr. #:
Manufacturer:
Infineon Technologies
Description:
MOSFET N-Ch 40V 50A DPAK-2 OptiMOS-T2
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet