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CAT28C16AGI12

P1-P3P4-P6P7-P9P10-P10
CAT28C16A
http://onsemi.com
4
Figure 2. A.C. Testing Input/Output Waveform (Note 11)
INPUT PULSE LEVELS REFERENCE POINTS
2.0 V
0.8 V
2.4 V
0.45 V
11. Input rise and fall times (10% and 90%) < 10 ns.
Figure 3. A.C. Testing Load Circuit (example)
1.3V
DEVICE
UNDER
TEST
1N914
3.3K
OUT
C
L
= 100 pF
C
L
INCLUDES JIG CAPACITANCE
Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (V
CC
= 5 V ±10%, unless otherwise specified.)
Symbol Parameter
28C16A−90 28C16A−12 28C16A−20
Units
Min Max Min Max Min Max
t
WC
Write Cycle Time 5 5 10 ms
t
AS
Address Setup Time 0 0 10 ns
t
AH
Address Hold Time 100 100 100 ns
t
CS
CE Setup Time 0 0 0 ns
t
CH
CE Hold Time 0 0 0 ns
t
CW
(Note 12) CE Pulse Time 110 110 150 ns
t
OES
OE Setup Time 0 0 15 ns
t
OEH
OE Hold Time 0 0 15 ns
t
WP
(Note 12) WE Pulse Width 110 110 150 ns
t
DS
Data Setup Time 60 60 50 ns
t
DH
Data Hold Time 0 0 10 ns
t
DL
Data Latch Time 5 10 5 10 50 ns
t
INIT
(Note 13) Write Inhibit Period After Power−up 0.05 100 0.05 100 5 20 ms
12.A write pulse of less than 20 ns duration will not initiate a write cycle.
13.This parameter is tested initially and after a design or process change that affects the parameter.
CAT28C16A
http://onsemi.com
5
DEVICE OPERATION
Read
Data stored in the CAT28C16A is transferred to the data bus when WE is held high, and both OE and CE are held low. The
data bus is set to a high impedance state when either CE or OE goes high. This 2−line control architecture can be used to
eliminate bus contention in a system environment.
Figure 4. Read Cycle
ADDRESS
DATA OUT DATA VALIDDATA VALID
HIGH−Z
t
OHZ
t
HZ
t
AA
t
OH
t
OE
t
OLZ
t
CE
t
LZ
t
RC
V
IH
CE
OE
WE
Figure 5. Byte Write Cycle [WE Controlled]
ADDRESS
DATA OUT
DATA IN
DATA VALID
HIGH−Z
WE
OE
CE
t
AH
t
AS
t
CS
t
CH
t
WP
t
OES
t
OEH
t
DL
t
DS
t
DH
t
WC
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either WE
or CE, with the address input being latched on the falling
edge of WE or CE, whichever occurs last. Data, conversely,
is latched on the rising edge of WE or CE, whichever occurs
first. Once initiated, a byte write cycle automatically erases
the addressed byte and the new data is written within 10 ms.
CAT28C16A
http://onsemi.com
6
DATA Polling
DATA polling is provided to indicate the completion of a
byte write cycle. Once a byte write cycle is initiated,
attempting to read the last byte written will output the
complement of that data on I/O
7
(I/O
0
–I/O
6
are
indeterminate) until the programming cycle is complete.
Upon completion of the self−timed byte write cycle, all I/O’s
will output true data during a read cycle.
Figure 6. Byte Write Cycle [CE Controlled]
ADDRESS
DATA OUT
DATA IN
DATA VALID
HIGH−Z
WE
OE
CE
t
AS
t
AH
t
CS
t
OES
t
CW
t
OEH
t
CH
t
DL
t
DS
t
DH
t
WC
Figure 7. DATA Polling
ADDRESS
I/O
7
WE
OE
CE
D
IN
= X
D
OUT
= X D
OUT
= X
t
OEH
t
OE
t
WC
t
OES
Hardware Data Protection
The following is a list of hardware data protection features
that are incorporated into the CAT28C16A.
1. V
CC
sense provides for write protection when V
CC
falls below 3.0 V min.
2. A power on delay mechanism, t
INIT
(see AC
characteristics), provides a 5 to 20 ms delay before
a write sequence, after V
CC
has reached 3.0 V
min.
3. Write inhibit is activated by holding any one of
OE low, CE high or WE high.
4. Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
P1-P3P4-P6P7-P9P10-P10

CAT28C16AGI12

Mfr. #:
Buy CAT28C16AGI12
Manufacturer:
ON Semiconductor
Description:
IC EEPROM 16K PARALLEL 32PLCC
Lifecycle:
New from this manufacturer.
Delivery:
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