4
COMMERCIAL TEMPERATURE RANGE
IDT728980 Time Slot Interchange Digital Switch
256 x 256
If the ODE input pin is LOW, then all the serial outputs are high-impedance.
If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH)
or disables (if LOW) the output stream and channel.
The contents of bit 1 (CCO) of each Connection Memory High Location (see
Table 4) is output on CCO pin once every frame. The CCO pin is a 2.048 Mb/s
output, which carries 256 bits. If CCO bit is set HIGH, the corresponding bit on
CCO output is transmitted HIGH. If CCO is LOW, the corresponding bit on the
CCO output is transmitted in LOW. The contents of the 256 CCO bits of the CMH
are transmitted sequentially on to the CCO output pin and are synchronous to
the TX streams. To allow for delay in any external control circuitry the contents
of the CCO bit is output one channel before the corresponding channel on the
TX streams. For example, the contents of CCO bit in position 0 (corresponding
to TX0, CH0) is transmitted synchronously with the TX channel 31, bit 7. Bit 1's
of CMH for channel 1 of stream 0-7 are output synchronously with TX channel
0 bits 7-0.
Table 2. Address Mapping
Connection Memory High
Connection Memory Low
Channel 0 Channel 1 Channel 2 Channel 31
Channel 0 Channel 1 Channel 2 Channel 31
Channel 0 Channel 1 Channel 2 Channel 31
Channel 0 Channel 1 Channel 2 Channel 31
Channel 0 Channel 1 Channel 2 Channel 31
Channel 0 Channel 1 Channel 2 Channel 31
Channel 0 Channel 1 Channel 2 Channel 31
Channel 0 Channel 1 Channel 2 Channel 31
100001 100010 111111
Data Memory
0 0 0
0
0 0
1
1
0 1 0
2
0 1 1 3
1 0
0 4
1 0
1 5
1 1 0 6
1 1 1 7
Stream
0 1
1
0
1 1
Control Register
CR
b
7
External Address Bits A5-A0
5706 drw07
100000
The Control Register is only accessed when A5=0.
All other address bits have no effect when A5=0.
When A5 =1, only 32 bytes are randomly accessable via
A0-A4 at any one instant. Which 32 bytes are
accessed is determined by the state of CRb0 -CRb4.
The 32 bytes correlate to 32 channel of one ST-BUS
®
stream.
CR
b
6CR
b
5CR
b
4CR
b
3CR
b
2CR
b
1CR
b
0
CR
b
4CR
b
3
CR
b
2CR
b
1CR
b
0
Table 1. Input Stream to Output Stream Combinations that can Provide the
Minimum 2-Channel Delay
Figure 3. Address Mapping
Input Output Stream
0 1,2,3,4,5,6,7
1 3,4,5,6,7
2 5,6,7
37
4 1,2,3,4,5,6,7
5 3,4,5,6,7
6 5,6,7
77
NOTES:
1. Writing to the Control Register is the only fast transaction.
2. Memory and stream are specified by the contents of the Control Register.
A5 A4 A3 A2 A1 A0 HEX ADDRESS LOCATION
0XXXXX 00-1F Control Register
(1)
100000 20 Channel 0
(2)
100001 21 Channel 1
(2)
•••••• • •
•••••• • •
•••••• • •
111111 3F Channel 31
(2)
INITIALIZATION OF THE IDT728980
On initialization or power up, the contents of the Connection Memory High
can be in any state. This is a potentially hazardous condition when multiple TX
outputs are tied together to form matrices. The ODE pin should be held low on
power up to keep all outputs in the high impedance condition until the contents
of the CMH are programmed.
During the microprocessor initialization routine, the microprocessor should
program the desired active paths through the matrices, and put all other channels
into the high impedance state. Care should be taken that no two connected TX
outputs drive the bus simultaneously. With the CMH setup, the microprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedance state control to the Connection Memory High bits outputs.
