35
4428E–8051–02/08
AT/TS80C31X2
Table 14-10. AC Parameters for a Variable Clock: derating formula
14.5.3 External Data Memory Write Cycle
Figure 14-7. External Data Memory Write Cycle
Symbol Type
Standard
Clock X2 Clock -M -V -L Units
T
RLRH
Min 6 T - x 3 T - x 20 15 25 ns
T
WLWH
Min 6 T - x 3 T - x 20 15 25 ns
T
RLDV
Max 5 T - x 2.5 T - x 25 23 30 ns
T
RHDX
Min x x 0 0 0 ns
T
RHDZ
Max 2 T - x T - x 20 15 25 ns
T
LLDV
Max 8 T - x 4T -x 40 35 45 ns
T
AVDV
Max 9 T - x 4.5 T - x 60 50 65 ns
T
LLWL
Min 3 T - x 1.5 T - x 25 20 30 ns
T
LLWL
Max 3 T + x 1.5 T + x 25 20 30 ns
T
AVWL
Min 4 T - x 2 T - x 25 20 30 ns
T
QVWX
Min T - x 0.5 T - x 15 10 20 ns
T
QVWH
Min 7 T - x 3.5 T - x 15 10 20 ns
T
WHQX
Min T - x 0.5 T - x 10 8 15 ns
T
RLAZ
Max x x 0 0 0 ns
T
WHLH
Min T - x 0.5 T - x 15 10 20 ns
T
WHLH
Max T + x 0.5 T + x 15 10 20 ns
T
QVWH
T
LLAX
ALE
PSEN
WR
PORT 0
PORT 2
A0-A7 DATA OUT
ADDRESS
OR SFR-P2
T
AVWL
T
LLWL
T
QVWX
ADDRESS A8-A15 OR SFR P2
T
WHQX
T
WHLH
T
WLWH