ICS9DB803D
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
IDT®
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2 8
ICS9DB803D REV N 071013
Electrical Characteristics–Input/Supply/Common Output Parameters
A
= Tambient for the desired operating range, Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage V
IHSE
DD
+ 0.3 V 1
Input Low Voltage V
ILSE
GND - 0.3 0.8 V 1
Input High Current I
IHSE
IN
DD
-5 5 uA 1
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors -5 uA 1
I
IL2
IN
= 0 V; Inputs with pull-up resistors -200 uA 1
I
DD3.3OPC
Full Active, C
L
= Full load; Commerical
Tem
Ran
e
175 200 mA 1
I
DD3.3OPI
Full Active, C
L
= Full load; Industrial
Tem
Ran
e
190 225 mA 1
all diff pairs driven, C-Temp 50 60 mA 1
all differential pairs tri-stated, C-Temp 4 6 mA 1
all diff pairs driven, I-temp 55 65 mA 1
all differential pairs tri-stated, I-temp 6 8 mA 1
I
DD3.3OPC
Full Active, C
L
= Full load; Commerical
Tem
Ran
e
105 125 mA 1
I
DD3.3OPI
Full Active, C
L
= Full load; Industrial
Tem
Ran
e
115 150 mA 1
all diff pairs driven, C-Temp 25 30 mA 1
all differential pairs tri-stated, C-Temp 2 3 mA 1
all diff pairs driven, I-Temp 30 35 mA 1
all differential pairs tri-stated, I-Temp 3 4 mA 1
F
iPLL
PCIe Mode (Bypass#/PLL= 1) 50 100 MHz 1
F
iBYPASS
Bypass Mode ((Bypass#/PLL= 0) 33 400 MHz 1
Pin Inductance L
in
IN
Logic Inputs, except SRC_IN 1.5 5 pF 1
C
INSRC_IN
SRC_IN differential clock inputs 1.5 2.7 pF 1,4
C
OUT
Output pin capacitance 6 pF 1
-3dB point in High BW Mode 2 3 4 MHz 1
-3dB point in Low BW Mode 0.7 1 1.4 MHz 1
PLL Jitter Peaking t
JPEAK
Peak Pass band Gain 1.5 2 dB 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st
clock
1ms1,2
Input SS Modulation
Frequency
f
MODIN
Allowable Frequency
(Triangular Modulation)
30 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1 3 cycles 1,3
Tdrive_SRC_STOP# t
DRVSTP
DIF output enable after
SRC_Stop# de-assertion
10 ns 1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of PD# and SRC_STOP# 5 ns 1
Trise t
Rise time of PD# and SRC_STOP# 5 ns 2
SMBus Voltage V
MAX
Maximum input voltage 5.5 V 1
Low-level Output Voltage V
OL
PULLUP
0.4 V 1
Current sinking at V
OL
PULLUP
4mA1
SCLK/SDATA
Clock/Data Rise Time
t
RSMB
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000 ns 1
SCLK/SDATA
Clock/Data Fall Time
t
FSMB
(Min VIH + 0.15) to
(Max VIL - 0.15)
300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 100 kHz 1,5
1
Guaranteed by design and characterization, not 100% tested in production.
2
See timing diagrams for timing requirements.
I
DD3.3PDI
I
DD3.3PDI
9DB803 Powerdown
Current
Single Ended Inputs, 3.3 V +/-5%
Input Low Current
I
DD3.3PDC
9DB803 Supply Current
9DB403 Supply Current
9DB403 Powerdown
Current
5
The differential input clock must be running for the SMBus to be active
Input Frequency
4
SRC_IN input
I
DD3.3PDC
3
Time from deassertion until outputs are >200 mV
PLL Bandwidth BW
Capacitance