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9DB803DGLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
ICS9DB803D
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
IDT®
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2 19
ICS9DB803D REV N 071013
Package Outline and Package Dimensions (48-pin TSSOP)
Package dimensions are kept current with JEDEC Publication No. 95
INDEX
AREA
1 2
48
D
E1
E
SEATING
PLANE
A1
A
A2
e
- C -
b
aaa C
c
L
*For reference only. Controlling dimensions in mm.
Millimeters Inches*
Symbol Min Max Min Max
A--1.20--0.047
A1 0.05 0.15 0.002 0.006
A2 0.80 1.05 0.032 0.041
b 0.17 0.27 0.007 0.011
c 0.09 0.20 0.0035 0.008
D 12.40 12.60 0.488 0.496
E 8.10 BASIC 0.319 BASIC
E1 6.00 6.20 0.236 0.244
e 0.50 Basic 0.020 Basic
L 0.45 0.75 0.018 0.030
0 8 0 8
aaa -- 0.10 -- 0.004
ICS9DB803D
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
IDT®
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2 20
ICS9DB803D REV N 071013
Package Outline and Package Dimensions (48-pin SSOP)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“D” is the device revision designator (will not correlate with the datasheet revision).
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
INDEX
AREA
1 2
48
D
E1
E
SEATING
PLANE
A1
A
A2
e
- C -
b
aaa C
c
L
*For reference only. Controlling dimensions in mm.
Millimeters Inches*
Symbol Min Max Min Max
A 2.412.80.095.110
A1 0.20 0.40 .008 .016
b 0.200.34.008.0135
c 0.130.25.005.010
D 15.75 16.00 .620 .630
E 10.03 10.68 .395 .420
E1 7.40 7.60 .291 .299
e 0.635 BASIC 0.025 BASIC
h 0.380.64.015.025
L 0.501.02.020.040
0 8 0 8
Part / Order Number Marking Shipping Packaging Package Temperature
9DB803DGLF 9DB803DGLF Tubes 48-pin TSSOP 0 to +70° C
9DB803DGLFT 9DB803DGLF Tape and Reel 48-pin TSSOP 0 to +70° C
9DB803DGILF 9DB803DGILF Tubes 48-pin TSSOP -40 to +85° C
9DB803DGILFT 9DB803DGILF Tape and Reel 48-pin TSSOP -40 to +85° C
9DB803DFLF 9DB803DFLF Tubes 48-pin SSOP 0 to +70° C
9DB803DFLFT 9DB803DFLF Tape and Reel 48-pin SSOP 0 to +70° C
9DB803DFILF 9DB803DFILF Tubes 48-pin SSOP -40 to +85° C
9DB803DFILFT 9DB803DFILF Tape and Reel 48-pin SSOP -40 to +85° C
ICS9DB803D
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
IDT®
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2 21
ICS9DB803D REV N 071013
Revision History
Rev. Issue Date Issuer Description Page #
A 8/15/2006 Updated electrical characteristics for final data sheet -
B Added Input Clock Specs
C 2/29/2008 Updated Input Clock Specs
D 3/18/2008
Fixed typo in Input Clock Parameters
E 3/28/2008 Updated Electrical Char tables
F 4/10/2008 Updated Input Clock Specs
G 1/13/2009 Corrected part ordering information
H 10/7/2009
1. Clarified that Vih and Vil values were for Single ended inputs
2. Added Differential Clock input parameters.
3. Updated Electrical Characteristics to add propagation delay and
phase noise information.
4. Added SMBus electrical characteristics
5. Added foot note about DIF input running in order for the SMBus
interface to work
6. Added foot note to Byte 1 about functionality of OE bits and OE
pins.
7. Updated/Reformatted General Description Various
J 1/27/2011 Updated Termination Figure 4 12
K 5/9/2011
1. Update pin 2 pin-name and pin description from VDD to VDDR. This
highlights that optimal peformance is obtained by treating VDDR as in
analog pin. This is a document update only, there is no silicon change.
Various
L 8/27/2012
Updated Vswing conditions to include "single-ended measurement"
7
M 9/18/2012
Updated Byte 2, bits 0~7 per char review. Outputs can be programmed
with Byte 2 to be Stoppable or Free-Run with DIF_Stop pin, not the OE
pins.
14
N 7/10/2013 R. Wei
Typo discovered on front page "Output Features" section. Was: “50 –
110
MHz operation in PLL mode”; changed to: "50 –
100
MHz operation
in PLL mode”
1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

9DB803DGLF

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Manufacturer:
IDT
Description:
Clock Buffer 8 OUTPUT PCIE GEN2 BUFFER
Lifecycle:
New from this manufacturer.
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