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ZL40208LDG1
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
ZL40208
Data Sheet
4
Microsemi Corporation
Change Summary
Page
Item
Change
7
8
Figure 5
Figure 6
Changed text to indicate the circuit is not reco
mmended for
VDD_dr
iver=2.5V
.
Changed pull-up and pull-
down resistors from 2kOhm to
10
0Ohm.
Below are the changes from the November 201
2 issue to the February 2013 issue:
ZL40208
Data Sheet
5
Microsemi Corporation
1.0 Package Description
The device is pa
ckaged in a 32 pin QFN
26
28
30
32
12
10
8
6
4
2
vdd
out5_p
out4_n
out5_n
NC
NC
clk0_n
clk0_p
out1_n
sel
out0_n
out1_p
gnd
out3_n
vdd
out2_p
14
16
18
22
24
20
gnd
vdd
out0_p
clk1_p
out2_n
NC
out3_p
vdd
clk1_n
out4_p
gnd
NC
gnd (E-p
ad)
NC
vdd
gnd
vdd
Figure 2 - Pin Connections
ZL40208
Data Sheet
6
Microsemi Corporation
2.0 Pin Description
Pin #
Name
Description
1, 4,
5, 8
clk0_p, clk0_n,
clk1_p, clk1_n
Differential Input (Analog Input).
Differential (or singled en
ded
) input signals. For all
input signal configuration
see Section 3.1, “Clock Inputs“.
29, 28,
27, 26,
22, 21,
20, 19,
15, 14,
13, 12
out0_p, out0_n
out1_p, out1_n
out2_p, out2_n
out3_p, out3_n
out4_p, out4_n
out5_p, out5_n
Differential Outpu
t (Analog Output).
Dif
ferential outputs.
1
1, 16,
18, 23,
25, 30
vdd
Positive Supply V
olt
age.
2.5V
DC
or 3.3 V
DC
nominal.
9, 17,
24, 32
gnd
Ground.
0 V
.
31
sel
Input Select (Input).
Selects the reference
input that is buf
fered;
0: clk0
1: clk1
This pin is internally
pulled down
to GND.
2, 3,
6, 7,
10
NC
No Connection.
L
eave unconnected.
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
ZL40208LDG1
Mfr. #:
Buy ZL40208LDG1
Manufacturer:
Microchip / Microsemi
Description:
Clock Buffer 2:6 LVPECL Fanout Buffer w/Ext. Term.
Lifecycle:
New from this manufacturer.
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