ADCMP609 Data Sheet
APPLICATIONS INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP609 comparator is a high speed device. Despite the
low noise output stage, it is essential to use proper high speed
design techniques to achieve the specified performance. Because
comparators are uncompensated amplifiers, feedback in any
phase relationship is likely to cause oscillations or undesired
hysteresis. Of critical importance is the use of low impedance
supply planes, particularly the output supply plane (V
CC
) and
the ground plane. Individual supply planes are recommended as
part of a multilayer board. Providing the lowest inductance return
path for switching currents ensures the best possible performance
in the target application.
It is also important to adequately bypass the input and output
supplies. Place a 0.1 µF bypass capacitor as close as possible to
each V
CC
supply pin. The capacitor should be connected to the
ground plane with redundant vias placed to provide a physically
short return path for output currents flowing back from ground
to the V
CC
pin. Carefully select high frequency bypass capacitors
for minimum inductance and effective series resistance (ESR).
Parasitic layout inductance should also be strictly controlled to
maximize the effectiveness of the bypass at high frequencies.
TTL-/CMOS-COMPATIBLE OUTPUT STAGE
To achieve specified propagation delay performance, keep the
capacitive load at or below the specified minimums. The
outputs of the ADCMP609 are designed to directly drive one
Schottky TTL or three low power Schottky TTL loads (or an
equivalent). For large fan outputs, buses, or transmission lines,
use an appropriate buffer to maintain the excellent speed and
stability of the comparator.
With the rated 15 pF load capacitance applied, more than half
of the total device propagation delay is output stage slew time.
Because of this, the total propagation delay decreases as V
CC
decreases, and instability in the power supply may appear as
excess delay dispersion.
Delay is measured to the 50% point for whatever supply is in
use; therefore, the fastest times are observed with the V
CC
supply at
2.5 V, and larger values are observed when driving loads that
switch at other levels.
Overdrive and input slew rate dispersions are not significantly
affected by output loading and V
CC
variations.
The TTL-/CMOS-compatible output stage is shown in the
simplified schematic diagram (Figure 11). Because of its
inherent symmetry and generally good behavior, this output
stage is readily adaptable for driving various filters and other
unusual loads.
OUTPUT
Q2
Q1
+IN
–IN
OUTPUT STAGE
V
LOGIC
GAIN STAGE
A2
A1
A
V
06918-011
Figure 11. Simplified Schematic Diagram of
TTL-/CMOS-Compatible Output Stage
OPTIMIZING PERFORMANCE
As with any high speed comparator, proper design and layout tech-
niques are essential for obtaining the specified performance. Stray
capacitance, inductance, common power and ground impedances,
or other layout issues can severely limit performance and often
cause oscillation. The source impedance should be minimized as
much as is practicable. High source impedance, in combination
with the parasitic input capacitance of the comparator, causes an
undesirable degradation in bandwidth at the input, therefore
degrading the overall response. Higher impedances encourage
undesired coupling.
COMPARATOR PROPAGATION DELAY DISPERSION
The ADCMP609 comparator is designed to reduce propagation
delay dispersion over a wide input overdrive range of 10 mV to
V
CC
− 1 V. Propagation delay dispersion is the variation in propa-
gation delay that results from a change in the degree of overdrive
or slew rate, which is how far or how fast the input signal
exceeds the switching threshold.
Propagation delay dispersion is a specification that becomes
important in high speed, time-critical applications, such as data
communication, automatic test and measurement, and instru-
mentation. It is also important in event-driven applications, such as
pulse spectroscopy, nuclear instrumentation, and medical imaging.
Dispersion is the variation in propagation delay as the input over-
drive conditions are changed (see Figure 12 and Figure 13).
ADCMP609 dispersion is typically <12 ns as the overdrive varies
from 10 mV to 125 mV. This specification applies to both positive
and negative signals because the device has very closely matched
delays for both positive-going and negative-going inputs, and very
low output skews. Note that for repeatable dispersion measure-
ments the actual device offset is added to the overdrive.
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