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72V255LA10PFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
19
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 10. Read Timing (First Word Fall Through Mode)
NOTES:
1. t
SKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than t
SKEW1, then the IR assertion may be delayed one extra WCLK cycle.
2. t
SKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAF. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than t
SKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.
3. LD = HIGH
4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
5. D = 8,193 for IDT72V255LA and 16,385 for IDT72V265LA.
WCLK
12
WEN
D
0 - D17
RCLK
tENS
REN
Q
0 - Q17
PAF
HF
PAE
IR
OR
W1 W1 W2 W3
Wm+2
W[m+3]
tOHZ
tSKEW1
tENH
tDS
tDH
tOE tA
tA
tA
tPAF
tWFF
tWFF
tENS
OE
tSKEW2
WD
4672 drw 13
tPAE
W[D-n]W[D-n-1]
tA tA
tHF
tREF
W[D-1]
WD
tA
W[D-n+1]W[m+4] W[D-n+2]
(1)
(2)
tENS
D-1
+ 1
][
W
2
D-1
+ 2
][
W
2
1
20
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D –2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 8,192 for IDT72V255LA and 16,384 for IDT72V265LA.
5. EF goes HIGH at 60 ns + 1 RCLK cycle + tREF.
Figure 11. Retransmit Timing (IDT Standard Mode)
t
REF
t
ENH
4672 drw14
t
A
t
ENS
W
x
WCLK
RCLK
REN
RT
EF
PAF
HF
PAE
Q
0
- Q
n
t
SKEW4
12
1
W
1
t
HF
t
PAE
t
REF
W
x+1
2
W
2
t
ENH
WEN
t
ENS
t
ENS
t
ENH
(3)
t
A
t
A
(3)
(5)
t
RTS
t
RTS
t
PAF
21
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D –2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup
procedure. D = 8,193 for the IDT72V255LA and 16,385 for the IDT72V265LA.
3. OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. OR goes LOW at 60 ns + 2 RCLK cycles + tREF.
Figure 12. Retransmit Timing (FWFT Mode)
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
REF
t
ENH
4672 drw15
t
ENS
W
x
WCLK
RCLK
REN
RT
OR
PAF
HF
PAE
Q
0 - Qn
t
SKEW4
12
1
t
HF
t
PAE
t
REF
W
x+1
2
W
2
t
ENH
WEN
t
ENS
W
1
t
ENH
(4)
(5)
3
4
t
ENH
W
3
t
RTS
t
RTS
t
PAF
t
A
t
A
NOTE:
1. X = 12 for the IDT72V255LA and X = 13 for the IDT72V265LA.
WCLK
SEN
SI
4672 drw 16
t
ENH
t
ENS
t
LDS
LD
t
DS
BIT 0
EMPTY OFFSET
BIT X
BIT 0
FULL OFFSET
(1)
t
ENH
BIT X
(1)
t
LDH
t
LDH
t
LDH
t
LDH
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

72V255LA10PFG

Mfr. #:
Buy 72V255LA10PFG
Manufacturer:
IDT
Description:
FIFO 8Kx18 3.3V SUPER SYNC FIFO
Lifecycle:
New from this manufacturer.
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