ADPD2210 Data Sheet
Rev. A | Page 12 of 15
APPLICATIONS INFORMATION
POWERING THE ADPD2210
The ADPD2210 is powered from a single positive 1.8 V to 5 V
supply, although performance below 2.5 V is limited by the
reduced dynamic range of the device. Above the quiescent
current (140 μA), the supply current has a linear relationship to
the output current: I
SUPPLY
= I
FLOOR
+ (3.3 × I
OUT
). The ADPD2210
features a 25 nA/V (typical) PSRR, but proper circuit layout and
bypassing is recommended to provide maximum sensitivity,
especially in designs where the ADPD2210 may share reference
nodes with transmitters in pulse mode applications.
EXPOSED PAD CONNECTION
The exposed pad (EPAD) on the ADPD2210 acts as an electri-
cal, thermal, and mechanical platform for the amplifier and
must be connected to a quiet GND. External cooling is not
required due to the extremely low power consumption of the
ADPD2210. Analog Devices, Inc., recommends removal of
active traces beneath the device to eliminate potential coupling
of external signals into the sensitive internal nodes of the
ADPD2210.
POWER-DOWN
The power-down pin does not have an internal pull-up/pull-down
circuit and must be connected to an external logic level for
proper operation.
In the recommended configuration and when it is not in power-
down mode, the ADPD2210 presents an approximate 90 Ω load
to the photodiode anode. This load limits the photovoltaic
effect from a silicon photodiode at full scale to approximately
900 μV. In the power-down state, the ADPD2210 presents a
high impedance at the IN pin and the photovoltaic effect from a
photodiode is limited to the open-circuit voltage of the
photodiode.
In applications where the ADPD2210 is fed from a current source,
initiation of power-down mode causes the voltage at the IN pin
to slew up to the compliance voltage of the current source. The
rate at which the voltage slews depends on the current sourced
and capacitance at the IN pin. If the compliance voltage of the
current source is significantly higher than the V
CC
− 2 × V
BE
voltage of the IN pin, the ADPD2210 requires additional settling
time to come out of the power-down state. V
BE
is the base
emitter voltage.
REFERENCE OUPUT
The REF pin is sensitive to loading and is not intended to drive
more than 1 μA. When the ADPD2210 REF output is connected
to the cathode of the photodiode, loading of the REF pin is limited
to the offset voltage (±5 mV), divided by the shunt resistance
(typically >1 GΩ) of the photodiode.
In applications where the REF output is used to provide an
external reference or a guarding voltage, the REF output must
be buffered. Failure to buffer the REF pin may adversely affect
linearity above 4 μA.
LAYOUT CONSIDERATIONS
Working with very low currents requires special attention in
layout to prevent error currents due to leakage, especially in
instrumentation applications where the ADPD2210 may be
located at a distance from the current source. In applications
that rely on dynamic signals, parasitic capacitance must be
controlled as seemingly insignificant capacitance becomes
problematic with nanoampere scale signals.
OUTPUT CONFIGURATION
The output of the ADPD2210 allows different configurations
depending on the application. The current gain of the ADPD2210
reduces the effect of surrounding interferers but, for best perfor-
mance, careful design and layout is still necessary to achieve
best performance. The effect of capacitance on the output must
be considered carefully regardless of configuration as bandwidth
and response time of the system can be limited simply by the
time required to charge and discharge parasitics.
Because the ADPD2210 is effectively a current source, the
ADPD2210 output voltage drifts up to its compliance voltage,
approximately 1.2 V below VCC, when connected to an inter-
face that presents a high impedance. The rate of this drift is
dependent on the ADPD2210 output current, parasitic capaci-
tance, and the impedance of the load. This drift can require
additional settling time in circuits following the ADPD2210 if
they are actively multiplexing the output of the ADPD2210 or
presenting a high impedance due to power cycling. For multi-
plexed systems, a current steering architecture may offer a
performance advantage over a break-before-make switch matrix.
ACCURACY IN CLINICAL APPLICATIONS
Even with perfectly calibrated electronics, it is important to
note there is no absolute in photoplethysmography measure-
ments because they are affected by other variables, including
high levels of carboxyhemoglobin or methemoglobin, density of
other chromophores such as melanin, and conditions that may
affect perfusion such as peripheral artery disease, shock, or
hypothermia. It is important that photoplethysmography, though
well suited for real-time monitoring, be supported in a clinical
environment with more accurate laboratory procedures such as
blood gas analysis.
Data Sheet ADPD2210
Rev. A | Page 13 of 15
3-WIRE VOLTAGE CONFIGURATION
The ADPD2210 can be used in a minimal 3-wire voltage
configuration, offering a compact solution with very few
components (see Figure 25). A shunt resistor (R
S
) sets the
transimpedance gain in front of the analog-to-digital converter
(ADC). This configuration allows flexibility in matching the
ADC converter full-scale input to the full-scale output of the
ADPD2210. The dynamic range of the interface is limited to
the compliance voltage of the ADPD2210.
No additional amplification is needed prior to the ADC. Response
time at the lower end of the range is limited by the ability of the
output current to charge the parasitic capacitance presented to
the output of the ADPD2210.
3-WIRE CURRENT MODE CONFIGURATION
When used in the 3-wire current mode configuration with a
photodiode (see Figure 25), the ADPD2210 is insensitive to load
resistance and can be used when the signal processing is further
from the sensor. EMI noise and shielding requirements are
minimized; however, cable capacitance has a direct effect on
bandwidth, making the 3-wire current mode configuration a
better choice for unshielded interfaces. The C
F
value must be
chosen carefully to eliminate stability and bandwidth degrada-
tion of the ADPD2210. Large capacitance around the feedback
loop of the TIA has a direct effect on the bandwidth of the system.
Figure 25. ADPD2210 Used in 3-Wire Short Cable Voltage Mode Configuration with a Shunt Resistor
Figure 26. ADPD2210 Used in 3-Wire Current Mode Configuration with a TIA
ADPD2210
CURRENT
AMPLIFIER
REF
IN
ADC AND
MICROPROCESSOR
3.3V
3.3V
R
S
GND
OUT
VCC
12286-021
VCC
OUT
GND
3.3V
C
F
R
F
TIA
3.3V
ADPD2210
CURRENT
AMPLIFIER
REF
IN
ADC AND
MICROPROCESSOR
0V TO V
CC
–0.75
12286-022
ADPD2210 Data Sheet
Rev. A | Page 14 of 15
EVALUATION BOARD
Figure 27 shows the evaluation board schematic. Figure 28 and Figure 29 show the evaluation board layout for the top and bottom layers,
respectively.
Figure 27. Evaluation Board Schematic
Figure 28. Evaluation Board Layout, Top Layer
Figure 29. Evaluation Board Layout, Bottom Layer
1
THE PWDN PIN MUST BE BIASED TO V
IL
FOR NORMAL OPERATION AND V
IH
FOR STANDBY.
2
R1D IS NOT NORMALLY INSTALLED BUT CAN BE POPULATED WITH A LOAD RESISTOR TO
GENERATE THE VOLTAGE OUTPUT.
ADPD2210
1
2
3
5
6
PWDN
OUT
GND
VCC
IN
REF
EPAD
V
POG
R1D
DNI
R2D
100k
C2D
1µF
C1D
0.01µF
D1D
4
12286-024
12286-025
12286-026

ADPD2210ACPZ-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
IC AMP LP ULTRA-LOW NOISE 6LFCSP
Lifecycle:
New from this manufacturer.
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