Document Number: 002-10222 Rev. *B Page 7 of 17
Read Operation
There are two basic types of read operations. They are current
address read and selective address read. In a current address
read, the CY15E004J uses the internal address latch to supply
the lower 8 address bits. In a selective read, the user performs a
procedure to set these lower address bits to a specific value.
Current Address & Sequential Read
As mentioned above the CY15E004J uses an internal latch to
supply the lower 8 address bits for a read operation. A current
address read uses the existing value in the address latch as a
starting place for the read operation. The system reads from the
address immediately following that of the last operation.
To perform a current address read, the bus master supplies a
slave address with the LSB set to a ‘1’. This indicates that a read
operation is requested. The page select bit in the slave address
specifies the block of memory that is used for the read operation.
After receiving the complete slave address, the CY15E004J will
begin shifting out data from the current address on the next clock.
The current address is the bit from the slave address combined
with the 8-bits that were in the internal address latch.
Beginning with the current address, the bus master can read any
number of bytes. Thus, a sequential read is simply a current
address read with multiple byte transfers. After each byte the
internal address counter will be incremented.
Note Each time the bus master acknowledges a byte, this
indicates that the CY15E004J should read out the next
sequential byte.
There are four ways to properly terminate a read operation.
Failing to properly terminate the read will most likely create a bus
contention as the CY15E004J attempts to read out additional
data onto the bus. The four valid methods are:
1. The bus master issues a no-acknowledge in the 9th clock
cycle and a STOP in the 10th clock cycle. This is illustrated in
the diagrams below. This is preferred.
2. The bus master issues a no-acknowledge in the 9th clock
cycle and a START in the 10th.
3. The bus master issues a STOP in the 9th clock cycle.
4. The bus master issues a START in the 9th clock cycle.
If the internal address reaches 1FFh, it will wrap around to 000h
on the next read cycle. Figure 9 and Figure 10 below show the
proper operation for current address reads.
Figure 8. Multi-Byte Write
S ASlave Address 0 Word Address A Data Byte A P
By Master
By F-RAM
Start Address & Data Stop
Acknowledge
Data ByteA
Figure 9. Current Address Read
S ASlave Address 1 Data Byte 1 P
By Master
By F-RAM
Start Address
Stop
Acknowledge
No
Acknowledge
Data
Figure 10. Sequential Read
S ASlave Address 1 Data Byte 1 P
By Master
By F-RAM
Start Address
Stop
Acknowledge
No
Acknowledge
Data
Data ByteA
Acknowledge