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HEF4046BP,652

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
HEF4046B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 18 November 2011 7 of 20
NXP Semiconductors
HEF4046B
Phase-locked loop
7. Limiting values
[1] For DIP16 package: P
tot
derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: P
tot
derates linearly with 8 mW/K above 70 C.
8. Recommended operating conditions
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 +18 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
DD
+ 0.5 V - 10 mA
V
I
input voltage 0.5 V
DD
+ 0.5 V
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
DD
+ 0.5 V - 10 mA
I
I/O
input/output current - 10 mA
I
DD
supply current - 50 mA
T
stg
storage temperature 65 +150 C
T
amb
ambient temperature 40 +85 C
P
tot
total power dissipation DIP16 package
[1]
-750mW
SO16 package
[2]
-500mW
P power dissipation per output - 100 mW
Table 4. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
DD
supply voltage 3 - 15 V
as fixed oscillator only 3 - 15 V
phase-locked loop operation 5 - 15 V
V
I
input voltage 0 - V
DD
V
T
amb
ambient temperature in free air 40 - +85 C
t/V input transition rise and fall rate for INH input
V
DD
= 5 V - - 3.75 s/V
V
DD
= 10 V - - 0.5 s/V
V
DD
= 15 V - - 0.08 s/V
HEF4046B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 18 November 2011 8 of 20
NXP Semiconductors
HEF4046B
Phase-locked loop
9. Static characteristics
[1] Pin 15 open; pin 5 at V
DD
; pins 3 and 9 at V
SS
; pin 14 open.
[2] Pin 15 open; pin 5 at V
DD
; pins 3 and 9 at V
SS
; pin 14 at V
DD
;input current pin 14 not included.
Table 5. Static characteristics
V
SS
= 0 V; V
I
= V
SS
or V
DD
unless otherwise specified.
Symbol Parameter Conditions V
DD
T
amb
= 40 C T
amb
= 25 C T
amb
= 85 C Unit
Min Max Min Max Min Max
V
IH
HIGH-level
input voltage
I
O
< 1 A 5 V 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - V
V
IL
LOW-level
input voltage
I
O
< 1 A 5 V - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 V
V
OH
HIGH-level
output voltage
I
O
< 1 A 5 V 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - V
V
OL
LOW-level
output voltage
I
O
< 1 A 5 V - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 V
I
OH
HIGH-level
output current
V
O
= 2.5 V 5 V - 1.7 - 1.4 - 1.1 mA
V
O
= 4.6 V 5 V - 0.52 - 0.44 - 0.36 mA
V
O
= 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA
V
O
= 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA
I
OL
LOW-level output
current
V
O
= 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA
V
O
= 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA
V
O
= 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA
I
I
input leakage current 15 V - 0.3 - 0.3 - 1.0 A
I
OZ
OFF-state
output current
output HIGH and
returned to V
DD
15 V - 1.6 - 1.6 - 12.0 A
output LOW and
returned to V
SS
15 V - 1.6 - 1.6 - 12.0 A
I
DD
supply current 5 V
[1]
--20---A
10 V
[1]
- - 300 - - - A
15 V
[1]
- - 750 - - - A
I
O
= 0 A 5 V
[2]
- 20 - 20 - 150 A
10 V
[2]
- 40 - 40 - 300 A
15 V
[2]
- 80 - 80 - 600 A
C
I
input capacitance for INH input - - - 7.5 - - pF
HEF4046B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 18 November 2011 9 of 20
NXP Semiconductors
HEF4046B
Phase-locked loop
10. Dynamic characteristics
Table 6. Dynamic characteristics
V
SS
= 0 V; T
amb
= 25
C; C
L
= 50 pF; input transition times
20 ns.
Symbol Parameter Conditions V
DD
Min Typ Max Unit
Phase comparators
R
I
input resistance SIG_IN input; at self-bias operating point 5 V - 750 - k
10 V - 220 - k
15 V - 140 - k
V
i(sens)
input voltage
sensitivity
SIG_IN input A.C. coupled; peak-to-peak
values; R1 = 10 k; R2 = ; C1 = 100 pF;
independent of the lock range
5 V - 150 - mV
10 V - 150 - mV
15 V - 200 - mV
V
IL
LOW-level input
voltage
SIG_IN and COMP_IN inputs, DC
coupled LOW; full temperature range
5 V--1.5V
10 V - - 3.0 V
15 V - - 4.0 V
V
IH
HIGH-level input
voltage
SIG_IN and COMP_IN inputs, D.C.
coupled HIGH; full temperature range
5 V3.5--V
10 V 7.0 - - V
15 V 11.0 - - V
I
IH
HIGH-level input
current
SIG_IN input; at V
DD
5 V - 7 - A
10 V - 30 - A
15 V - 70 - A
I
IL
LOW-level input
current
SIG_IN input; at V
SS
5 V - 3- A
10 V - 18 - A
15 V - 45 - A
VCO
P power dissipation f
0
= 10 kHz; R1 = 1 M; R2 = ;
VCO_IN at 0.5 V
DD
; see Figure 10 to 12
5 V - 150 - W
10 V - 2500 - W
15 V - 9000 - W
f
max
maximum frequency VCO_IN at V
DD
;
R1 = 10 k;R2=; C1 = 50 pF
5 V 0.5 1.0 - MHz
10 V 1.0 2.0 - MHz
15 V 1.3 2.7 - MHz
f/T frequency variation
with temperature
no frequency offset (f
min
= 0 Hz) 5 V
[1]
-0.22 to
0.30
-%Hz/C
10 V
[1]
-0.04 to
0.05
-%Hz/C
15 V
[1]
-0.01 to
0.05
-%Hz/C
with frequency offset (f
min
> 0 Hz) 5 V
[1]
- 0 to
0.22
-%Hz/C
10 V
[1]
- 0 to
0.04
-%Hz/C
15 V
[1]
- 0 to
0.01
-%Hz/C
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HEF4046BP,652

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Buy HEF4046BP,652
Manufacturer:
NXP Semiconductors
Description:
Phase Locked Loops - PLL PHASE LOCKED LOOP W/VCO
Lifecycle:
New from this manufacturer.
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