REV. 0
–12–
AD725
system, the internal 4FSC (14.318 180 MHz) clock that drives
the VGA controller can be used for 4FSC on the AD725. This
signal is not directly accessible from outside the computer, but it
does appear on the VGA card. (A 1FSC-input encoder, the
AD724, is also available.)
If a separate RGB monitor is also to be used, it is not possible to
simply connect it to the R, G and B signals. The monitor pro-
vides a termination that would double terminate these signals.
The R, G, and B signals should be buffered by three amplifiers
with high input impedances. These should be configured for a
gain of two, which is normalized by the divide by two termina-
tion scheme used for the RGB monitor.
The AD8073 is a low cost triple video amplifier that can pro-
vide the buffering required in this application. However, since
the R, G and B signals go all the way to ground during horizon-
tal sync, the AD8073 will require a –5 V supply to handle these
signals. To be able to buffer the R, G and B signals using a
single supply, a rail-to-rail amplifier is required. In this applica-
tion, the AD8051 (single) and AD8052 (dual) can be used to
provide the three required channels. These can be operated on a
single supply of 3 V to 5 V.
Displaying VGA Output on a TV
The AD725 can be used to convert the analog RGB output from a
personal computer’s VGA card to the NTSC or PAL television
standards. To accomplish this it is important to understand that
the AD725 requires interlaced RGB video and clock rates that
are consistent with those required by the television standards.
In most computers the default output is a noninterlaced RGB
signal at a frame rate higher than used by either NTSC or PAL.
Most VGA controllers support a wide variety of output modes
that are controlled by altering the contents of internal registers.
It is best to consult with the VGA controller manufacturer to
determine the exact configuration required to provide an inter-
laced output at 60 Hz (50 Hz for PAL).
Figure 19 shows a circuit for connection to the VGA port of a
PC. The RGB outputs are ac coupled to the respective inputs of
the AD725. These signals should each be terminated to ground
with 75 .
The standard 15-pin VGA connector has HSYNC on Pin 13
and VSYNC on Pin 14. These signals also connect directly to
the same name signals on the AD725. For a synchronous NTSC
75V
75V
–5V
4FSC
+5V
0.1mF
+5V (V
AA
)
AGND
DGND
AD725
CE
RIN
GIN
BIN
HSYNC
VSYNC
CRMA
LUMA
CMPS
APOS
DPOS
0.1mF
10mF
0.1mF
10mF
75V75V
75V
220mF
COMPOSITE
VIDEO
75V
220mF
75V
220mF
Y
C
S-VIDEO
(Y/C VIDEO)
75V
75V
75V
B
G
R
RGB MONITOR
VSYNC
HSYNC
FROM VGA PORT
+5V
POWER DOWN
75V
+5V
VGA OUTPUT
CONNECTOR
14
15
16
6
7
8
9
10
11
4
5
1kV1kV
13
2
0.1mF
0.1mF
0.1mF
OSC
4FSC CLOCK
14.318180MHz (NTSC)
OR
17.734475MHz (PAL)
1/3
AD8073
75V
1kV1kV
1/3
AD8073
1/3
AD8073
1kV1kV
68mH
STND
YTRAP
18pF
9pF
0.1mF
47kV
1N4148
NTSC/PAL
0.1mF
Figure 19. Interfacing the AD725 to the (Interlaced) VGA Port of a PC
AD725
REV. 0
–13–
Low Cost Crystal Oscillator
A low cost oscillator can be made that provides a CW clock that
can be used to drive both the AD725 4FSC and other devices in
the system that require a clock at this frequency. Figure 20 shows a
circuit that uses one inverter of a 74HC04 package to create a
crystal oscillator and another inverter to buffer the oscillator
and drive other loads. The logic family must be a CMOS type
that can support the frequency of operation, and it must NOT
be a Schmitt trigger type of inverter. Resistor R1 from input to
output of U1A linearizes the inverter’s gain such that it provides
useful gain and a 180 degree phase shift to drive the oscillator.
R1
1MV
Y1
TO PIN 3
OF AD725
U1A
U1B
R2
200V
C2
60pF
C1
47pF
C3
~
15pF
(OPT)
TO OTHER
DEVICE CLOCKS
HC04 HC04
Figure 20. Low Cost Crystal Oscillator
The crystal should be a parallel resonant type at the appropriate
frequency (NTSC/PAL, 4FSC). The series combination of C1
and C2 should approximately equal to the crystal manufacturer’s
specification for the parallel capacitance required for the crystal
to operate at its specified frequency. C1 will usually want to be
a somewhat smaller value because of the input parasitic capaci-
tance of the inverter. If it is desired to tune the frequency to
greater accuracy, C1 can be made still smaller and a parallel
adjustable capacitor can be used to adjust the frequency to the
desired accuracy.
Resistor R2 serves to provide the additional phase shift
required by the circuit to sustain oscillation. It can be sized by
R2 = 1/(2 × π × f × C2). Other functions of R2 are to provide a
low pass filter that suppresses oscillations at harmonics of the
fundamental of the crystal and to isolate the output of the in-
verter from the resonant load that the crystal network presents.
The basic oscillator described above is buffered by U1B to drive
the AD725 4FSC pin and other devices in the system. For a
system that requires both an NTSC and PAL oscillator, the
circuit can be duplicated by using a different pair of inverters
from the same package.
Dot Crawl
There are numerous distortions that are apparent in the presen-
tation of composite signals on TV monitors. These effects will
vary in degree depending on the circuitry used by the monitor
to process the signal and on the nature of the image being dis-
played. It is generally not possible to produce pictures on a
composite monitor that are as high quality as those produced by
standard quality RGB, VGA monitors.
One well known distortion of composite video images is called
dot crawl. It shows up as a moving dot pattern at the interface
between two areas of different color. It is caused by the inability
of the monitor circuitry to adequately separate the luminance
and chrominance signals.
One way to prevent dot crawl is to use a video signal that has
separate luminance and chrominance. Such a signal is referred
to as S-video or Y/C video. Since the luminance and chromi-
nance are already separated, the monitor does not have to per-
form this function. The S-video outputs of the AD725 can be
used to create higher quality pictures when there is an S-video
input available on the monitor.
Flicker
In a VGA conversion application, where the software controlled
registers are correctly set, there are two techniques that are
commonly used by VGA controller manufacturers to generate
the interlaced signal. Each of these techniques introduces a
unique characteristic into the display created by the AD725.
The artifacts described below are not due to the encoder or its
encoding algorithm as all encoders will generate the same dis-
play when presented with these inputs. They are due to the
method used by the controller display chip to convert a non-
interlaced output to an interlaced signal.
The first interlacing technique outputs a true interlaced signal
with odd and even fields (one each to a frame Figure 21a). This
provides the best picture quality when displaying photography,
CD video and animation (games, etc.). However, it will intro-
duce a defect commonly referred to as flicker into the display.
Flicker is a fundamental defect of all interlaced displays and is
caused by the alternating field characteristic of the interlace
technique. Consider a one pixel high black line which extends
horizontally across a white screen. This line will exist in only
one field and will be refreshed at a rate of 30 Hz (25 Hz for
PAL). During the time that the other field is being displayed the
line will not be displayed. The human eye is capable of detect-
ing this, and the display will be perceived to have a pulsating or
flickering black line. This effect is highly content sensitive and
is most pronounced in applications in which text and thin
horizontal lines are present. In applications such as CD video,
photography and animation, portions of objects naturally
occur in both odd and even fields and the effect of flicker is
imperceptible.
The second commonly used technique is to output an odd and
even field that are identical (Figure 21b). This ignores the data
that naturally occurs in one of the fields. In this case the same
one pixel high line mentioned above would either appear as a
two pixel high line, (one pixel high in both the odd and even field)
or not appear at all if it is in the data that is ignored by the control-
ler. Which of these cases occurs is dependent on the placement
of the line on the screen. This technique provides a stable (i.e.,
nonflickering) display for all applications, but small text can be
difficult to read and lines in drawings (or spreadsheets) can
disappear. As above, graphics and animation are not particularly
affected although some resolution is lost.
There are methods to dramatically reduce the effect of flicker and
maintain high resolution. The most common is to ensure that
display data never exists solely in a single line. This can be accom-
plished by averaging/weighting the contents of successive/multiple
noninterlaced lines prior to creating a true interlaced output (Fig-
ure 21c). In a sense, this provides an output that will lie between
the two extremes described above. The weight or percentage of
one line that appears in another, and the number of lines used,
are variables that must be considered in developing a system of
this type. If this type of signal processing is performed, it must
be completed prior to the data being presented to the AD725
for encoding.
REV. 0
–14–
AD725
Vertical Scaling
In addition to converting the computer generated image from
noninterlaced to interlaced format, it is also necessary to scale
the image down to fit into NTSC or PAL format. The most
common vertical lines/screen for VGA display are 480 and 600
lines. NTSC can only accommodate approximately 400 visible
lines/frame (200 per field), PAL can accommodate 576 lines/
frame (288 per field). If scaling is not performed, portions of
the original image will not appear in the television display.
This line reduction can be performed by merely eliminating
every Nth (6th line in converting 480 lines to NSTC or every
25th line in converting 600 lines to PAL). This risks generation
of jagged edges and jerky movement. It is best to combine the
scaling with the interpolation/averaging technique discussed
above to ensure that valuable data is not arbitrarily discarded in
the scaling process. Like the flicker reduction technique men-
tioned above, the line reduction must be accomplished prior to
the AD725 encoding operation.
There is a new generation of VGA controllers on the market
specifically designed to utilize these techniques to provide a
crisp and stable display for both text and graphics oriented
applications. In addition these chips rescale the output from the
computer to fit correctly on the screen of a television. A list of
known devices is available through Analog Devices’ Applica-
tions group, but the most complete and current information will
be available from the manufacturers of graphics controller ICs.
Synchronous vs. Asynchronous Operation
The source of RGB video and synchronization used as an input
to the AD725 in some systems is derived from the same clock
signal as used for the AD725 subcarrier input (4FSC). These
systems are said to be operating synchronously. In systems
where two different clock sources are used for these signals, the
operation is called asynchronous.
The AD725 supports both synchronous and asynchronous
operation, but some minor differences might be noticed be-
tween them. These can be caused by some details of the inter-
nal circuitry of the AD725.
There is an attempt to process all of the video and synchroniza-
tion signals totally asynchronous with respect to the subcarrier
signal. This was achieved everywhere except for the sampled
delay line used in the luminance channel to time align the lumi-
nance and chrominance. This delay line uses a signal at eight
times the subcarrier frequency as its clock.
The phasing between the delay line clock and the luminance
signal (with inserted composite sync) will be constant during
synchronous operation, while the phasing will demonstrate a
periodic variation during asynchronous operation. The jitter of
the asynchronous video output will be slightly greater due to
these periodic phase variations.
1
2
2
1
33
44
5
6
5
6
7
7
=+
NONINTERLACED ODD FIELD EVEN FIELD
a. Conversion of Noninterlace to Interlace
2
1
3
4
5
6
7
=
+
NONINTERLACED ODD FIELD EVEN FIELD
1
2
3
4
5
6
7
b. Line Doubled Conversion Technique
2
1
3
4
5
6
7
=+
NONINTERLACED ODD FIELD EVEN FIELD
1
2
3
4
5
6
7
c. Line Averaging Technique
Figure 21.
LUMA TRAP-THEORY
The composite video output of the AD725 can be improved for
some types of images by incorporating a luma trap (or Y-Trap)
in the encoder circuit. The basic configuration for such a circuit
is a notch or band elimination filter that is centered at the
subcarrier frequency. The luma trap is only functional for the
composite video output of the AD725; it has no influence on
the S-Video (or Y/C-Video) output.
The need for a luma trap arises from the method used by com-
posite video to encode the color part (chrominance or chroma)
of the video signal. This is performed by amplitude and phase
modulation of a subcarrier. The saturation (or lack of dilution of
a color with white) is represented in the subcarrier’s amplitude
modulation, while the hue (or color as thought of as the sections
of a rainbow) information is contained in the subcarrier’s phase
modulation. The modulated subcarrier occupies a bandwidth
somewhat greater than 1 MHz depending on the video standard.
For a composite signal, the chroma is linearly added to the
luminance (luma or brightness) plus sync signal to form a single
composite signal with all of the picture information. Once this
addition is performed, it is no longer possible to ascertain which
component contributed which part of the composite signal.
At the receiver, this single composite signal must be separated
into its various parts to be properly processed. In particular, the
chroma must be separated and then demodulated into its or-
thogonal components, U and V. Then, along with the luma
signal, the U and V signals generate the RGB signals that con-
trol the three video guns in the monitor.
A basic problem arises when the luma signal (which contains no
color information) contains frequency components that fall

AD725ARZ-R7

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Analog Devices Inc.
Description:
Video ICs RGB-NTSC/PAL ENCODER
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