AD725
REV. 0
–11–
The AD725 will operate with subcarrier frequencies that deviate
quite far from those specified by the TV standards. However,
the monitor will in general not be quite so forgiving. Most moni-
tors can tolerate a subcarrier frequency that deviates several hun-
dred Hz from the nominal standard without any degradation in
picture quality. These conditions imply that the subcarrier fre-
quency accuracy is a system specification and not a specification
of the AD725 itself.
The STND pin is used to select between NTSC and PAL opera-
tion. Various blocks inside the AD725 use this input to program
their operation. Most of the more common variants of NTSC and
PAL are supported. There are, however, two known specific stan-
dards which are not supported by the standard AD725. These are
NTSC 4.43 and M-PAL.
Basically these two standards use most of the features of the
standard that their names imply, but use the subcarrier that is
equal to or approximately equal to the frequency of the other
standard. Because of the automatic programming of the filters in
the chrominance path and other timing considerations, a factory-
programmed special version of the AD725 is necessary to sup-
port these standards.
Layout Considerations
The AD725 is an all CMOS mixed signal part. It has separate
pins for the analog and digital +5 V and ground power supplies.
Both the analog and digital ground pins should be tied to the
ground plane by a short, low inductance path. Each power
supply pin should be bypassed to ground by a low inductance
0.1 µF capacitor and a larger tantalum capacitor of about 10 µF.
The three analog inputs (RIN, GIN, BIN) should be terminated
with 75 Ω to ground close to the respective pins. However, as
these are high impedance inputs, they can be in a loop-through
configuration. This technique is used to drive two or more
devices with high frequency signals that are separated by some
distance. A connection is made to the AD725 with no local
termination, and the signals are run to another distant device
where the termination for these signals is provided.
The output amplitudes of the AD725 are double that required
by the devices that it drives. This compensates for the halving of
the signal levels by the required terminations. A 75 Ω series
resistor is required close to each AD725 output, while 75 Ω to
ground should terminate the far end of each line.
The outputs have a dc bias and must be ac coupled for proper
operation. The COMP and LUMA outputs have information
down to 30 Hz for NTSC (25 MHz for PAL) that must be trans-
mitted. Each output requires a 220 µF series capacitor to work
with the 75 Ω resistance to pass these low frequencies. The CRMA
signal has information mostly up at the chroma frequency and
can use a smaller capacitor if desired, but 220 µF can be used to
minimize the number of different components used in the design.
APPLYING THE AD725
Inputs
RIN, BIN, GIN are analog inputs that should be terminated to
ground with 75 Ω in close proximity to the IC. When properly
terminated the peak-to-peak voltage for a maximum input level
should be 714 mV p-p. The horizontal blanking interval should
be the most negative part of each signal.
The inputs should be held at the input signal’s black level dur-
ing the horizontal blanking interval. The internal dc clamps will
clamp this level during color burst to a reference that is used
internally as the black level. Any noise present on the RIN,
GIN, BIN or AGND pins during this interval will be sampled
onto the input capacitors. This can result in varying dc levels
from line to line in all outputs, or if imbalanced, subcarrier
feedthrough in the COMP and CRMA outputs.
For increased noise rejection, larger input capacitors are desired.
A capacitor of 0.1 µF is usually adequate.
Similarly, the U and V clamps balance the modulators during an
interval shortly after the falling CSYNC input. Noise present
during this interval will be sampled in the modulators, resulting
in residual subcarrier in the COMP and CRMA outputs.
HSYNC and VSYNC are two logic level inputs that are com-
bined internally to produce a composite sync signal. If a com-
posite sync signal is to be used, it can be input to HSYNC while
VSYNC is pulled to logic HI (> +2 V).
The form of the input sync signal(s) will determine the form of
the composite sync on the composite video (COMP) and lumi-
nance (LUMA) outputs. If no equalization or serration pulses
are included in the HSYNC input there won’t be any in the
outputs. Although sync signals without equalization and serra-
tion pulses do not technically meet the video standards’ specifi-
cations, many monitors do not require these pulses in order to
display good pictures. The decision whether to include these
signals is a system trade-off between cost and complexity and
adhering strictly to the video standards.
The HSYNC and VSYNC logic inputs have a small amount of
built-in hysteresis to avoid interpreting noisy input edges as
multiple sync edges. This is critical to proper device operation, as
the sync pulses are timed for vertical blanking interval detection.
The logic inputs have been designed for VIL < 1.0 V and VIH
> 2.0 V for the entire temperature and supply range of opera-
tion. This allows the AD725 to directly interface to TTL or 3 V
CMOS compatible outputs, as well as 5 V CMOS outputs
where VOL is less than 1.0 V.
The NTSC specification calls for a frequency accuracy of ±10 Hz
from the nominal subcarrier frequency of 3.579545 MHz. While
maintaining this accuracy in a broadcast studio might not be a
severe hardship, it can be quite expensive in a low cost con-
sumer application.
