MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
_______________________________________________________________________________________
7
Pin Description
NAME FUNCTION
1 OUT DAC Voltage Output
2 GND Ground
PIN
3 V
DD
Power-Supply Input
4 SDA Serial Data Input
5 SCL Serial Clock Input
10
μ
s/div
MAX5360
OUTPUT VOLTAGE
EXITING SHUTDOWN
MAX5360/1/2-19
OUT
500mV/div
SDA
3V/div
1
μ
s/div
MAX5360
OUTPUT VOLTAGE
ENTERING SHUTDOWN
MAX5360/1/2-20
OUT
500mV/div
SDA
3V/div
1
μ
s/div
MAX5360
OUTPUT SETTLING FROM
1/4 FS TO 3/4 FS
MAX5360/1/2-21
OUT
0.5V/div
SDA
3V/div
1
μ
s/div
MAX5360
OUTPUT SETTLING FROM
3/4 FS TO 1/4 FS
MAX5360/1/2-22
OUT
0.5V/div
SDA
3V/div
2
μ
s/div
MAX5360
OUTPUT SETTLING
1/4LSB STEP-UP
MAX5360/1/2-23
OUT
20mV/div
AC-COUPLED
SDA
3V/div
0 x 7F TO 0 x 80
01111111 TO 10000000
MAX5360
OUTPUT SETTLING
1/4LSB STEP-DOWN
MAX5360/1/2-24
OUT
20mV/div
AC-COUPLED
SDA
3V/div
2
μ
s/div
0 x 80 TO 0 x 7F
10000000 TO 01111111
Typical Operating Characteristics (continued)
(V
DD
= 3V (MAX5360), V
DD
= 5V (MAX5361/MAX5362), T
A
= +25°C, unless otherwise noted.)
MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
8 _______________________________________________________________________________________
Detailed Description
The MAX5360/MAX5361/MAX5362 voltage-output, 6-bit
DACs offer full 6-bit performance with less than 1LSB
integral nonlinearity (INL) error and less than 1LSB dif-
ferential nonlinearity (DNL) error ensuring monotonic
performance. The devices use a simple two-wire, fast-
mode I
2
C-compatible serial interface that operates up
to 400kHz. The MAX5360/MAX5361/MAX5362 include
an internal reference, an output buffer, and low-current
shutdown mode, making them ideal for low-power,
highly integrated applications. Figure 1 shows the
devices’ functional diagram.
Analog Section
The MAX5360/MAX5361/MAX5362 employ a current-
steering DAC topology as shown in Figure 2. At the
core of the DAC is a reference voltage-to-current con-
verter (V/I) that generates a reference current. This cur-
rent is mirrored to 255 equally weighted current
sources. DAC switches control the outputs of these cur-
rent mirrors, so only the desired fraction of the total cur-
rent-mirror currents is steered to the DAC output. The
current is then converted to a voltage across a resistor,
and this voltage is buffered by the output buffer amplifier.
Output Voltage
Table 1 shows the relationship between the DAC code
and the analog output voltage. The 6-bit DAC code is
binary unipolar with 1LSB = (V
REF
/ 64). The MAX5360/
MAX5361 have a full-scale output voltage of (+2V -
1LSB) and (+4V - 1LSB), respectively, set by the inter-
nal references. The MAX5362 has a full-scale output
voltage of (0.9
V
DD
- 1LSB). Each device accepts 8-bit
DAC codes, but the accuracy is guaranteed only for
6 bits.
Output Buffer
The DAC voltage output is an internally buffered unity-
gain follower that typically slews at ±0.4V/µs. The out-
put can swing from 0 to full scale. With a 1/4 FS to 3/4
FS output transition, the amplifier outputs typically settle
to 1/2LSB in less than 5µs when loaded with 10kΩ in
parallel with 50pF. The buffer amplifiers are stable with
any combination of resistive loads >10kΩ and capaci-
tive loads <50pF.
V
REF
OUT
SW1 SW2 SW255
Figure 2. Current-Steering Topology
V
DD
OUT
10k
GND
SDA
SCL
255
6 + 2
CURRENT-
STEERING
DAC
DATA LATCH
SERIAL INPUT
REGISTER
CONTROL
LOGIC
MAX5360
MAX5361
MAX5362
REF
Figure 1. Functional Diagram
Table 1. Unipolar Code Current
000001 (00) 0.9
V
DD
/ 6462mV31mV
000000 (00) 000
100000 (00) 0.9
V
DD
/ 22V1V
111111 (00) 0.9
V
DD
(63/64)4V
(63/64)2V
(63/64)
MAX5362
MAX5361
MAX5360
DAC CODE
6 BITS + 2 SUBBITS
OUTPUT VOLTAGE
MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
_______________________________________________________________________________________ 9
Power-On Reset
The MAX5360/MAX5361/MAX5362 have a power-on
reset circuit to set the DAC’s output to 0 when V
DD
is
first applied or when V
DD
dips below 1.7V. This ensures
that unwanted DAC output voltages will not occur
immediately following a system startup, such as after a
loss of power. The output glitch on startup is typically
<50mV.
Shutdown Mode
The MAX5360/MAX5361/MAX5362 include a software-
controlled shutdown mode that reduces the supply cur-
rent to <1µA. All internal circuitry is disabled and an
internal 10kΩ resistor is placed from OUT to GND to
ensure 0V at OUT while in shutdown. The device enters
shutdown in less than 5µs and exits shutdown in less
than 50µs.
Digital Section
Serial interface
The MAX5360/MAX5361/MAX5362 use a simple two-
wire serial interface requiring only two I/O lines (two-
wire bus) of a standard microprocessor (µP) port.
Figure 3 shows the timing diagram for signals on the 2-
wire bus.
The two bus lines (SDA and SCL) must be high when
the bus is not in use. The MAX5360/MAX5361/
MAX5362 are receive-only devices (slaves) and must
be controlled by a bus master device. Figure 4 shows a
typical application where multiple devices can be con-
nected to the bus provided they have different address
settings. External pullup resistors are not necessary on
these lines (when driven by push-pull drivers), though
the MAX5360/MAX5361/MAX5362 can be used in
applications where pullup resistors are required (such
as in I
2
C systems) to maintain compatibility with exist-
ing circuitry. The serial interface operates at SCL rates
up to 400kHz. The SDA state is allowed to change only
while SCL is low, with the exception of START and
STOP conditions as shown in Figure 5. Each transmis-
sion consists of a START condition sent by the bus
master device, followed by the MAX5360/MAX5361/
MAX5362’s preset slave address, a power-mode bit,
the DAC data (6 bits + 2 subbits), and finally, a STOP
SCL
SDA
t
LOW
t
HIGH
t
F
t
R
t
HD
,
STA
t
HD
,
DAT
t
HD
,
STA
t
SU
,
DAT
t
SU
,
STA
t
BUF
t
SU
,
STO
START CONDITIONSTOP CONDITIONREPEATED START CONDITIONSTART CONDITION
Figure 3. Two-Wire Serial Interface Timing Diagram
μC
SDA SCL
R
S
*
V
DD
OFFSET ADJUSTMENT
THRESHOLD ADJUSTMENT
GAIN ADJUSTMENT
R
S
* IS OPTIONAL.
SCL
SDA
V
DD
OUT
MAX5360M
2V REFERENCE
SCL
SDA
V
DD
OUT
MAX5361N
4V REFERENCE
SCL
SDA
V
DD
OUT
MAX5362P
V
DD
REFERENCE
Figure 4. Typical Application Circuit

MAX5360NEUK+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 6-Bit Precision DAC
Lifecycle:
New from this manufacturer.
Delivery:
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