Digital Multi-Phase GPU Buck Controller
October 12, 2011 | FINAL | V1.05
FEATURES
GPU-compliant Digital PWM Controller
Programmable 1-phase to 6-phase operation
Configurable switching frequency from 200 kHz to
1MHz per phase with accuracy better than 2%
IR Dynamic Phase Control
1-phase to 2-phase PSI for Light Loads
Adaptive Transient Algorithm minimizes output
bulk capacitors
Enables Thermal Phase Balancing
SMBus interface for configuring and monitoring
Compatible with IR ATL Drivers and
Tri-state Drivers
Nine bytes of NVM storage available for
customer use
+3.3V supply voltage; 0ºC to 85ºC Ambient
operation
RoHS Compliant, MSL level 1 package
APPLICATIONS
High performance GPU Voltage
Regulation solutions
High Current and High-Efficiency Applications
BASIC APPLICATION
PWM1
12V
V_GPU
ISEN1
IRTN1
3.3V
SV_DIO
ENABLE
ENABLE
SV_CLK
CHL8266
VR_RDY
VR_HOT#
PWM2
ISEN2
IRTN2
PWM4
ISEN4
IRTN4
Power
Stage 5
.
.
.
VCC
PWM1_L2
ISEN1_L2
IRTN1_L2
Power
Stage 2
Power
Stage 1
VR_RDY
VR_HOT#
SDA
SCL
Power
Stage 6
Figure 1: CHL8266 Basic Application Circuit
DESCRIPTION
The CHL8266 is a 6-phase digital synchronous buck
controller for regulation of high-performance GPU
platforms. The CHL8266 output VID table is fully compliant
with VR11.1 specifications.
The CHL8266 deploys a number of efficiency shaping
features. PSI can be programmed to be up to four phases
for optimum light-load efficiency, and the controller can
autonomously add/drop phases from mid to high and back
to mid current ranges to deliver 90+% efficiency across the
entire load range.
IR’s unique Adaptive Transient Algorithm, based on non-
linear digital PWM algorithms, minimizes output bulk
capacitors.
CHL8266 supports NTC temperature sense to report
temperature and trigger VR HOT and OTP faults. Digital
thermal balancing allows proportional current imbalance
between phases.
The CHL8266 provides extensive OVP, UVP, OCP and OTP
fault protection. Device and fault configuration parameters
are easily defined using the IR Digital Power Design Center
(DPDC) GUI and stored in on-chip non-volatile memory
(NVM).
The 2-pin SMBus interface can be used to monitor a variety
of operating parameters on CHL8266 based VRs.
The CHL8266 truly simplifies VRD design and enables
fastest time-to-market with its “set-and-forget”
methodology.
PIN DIAGRAM
SDA
PWM5
ISEN6
EN
VRTN
RCSM
PSI#
ISEN5
ISEN4
ISEN3
PWM6
TP3
VID1
VID2
VID3
VID4
VID5
TP4
TP5
VGPU
VCC
SCL
PWM4
TP2
VR_READY
IRTN3
IRTN4
IRTN6
IRTN5
RCSP
TSEN
VR_HOT
PWM3
VINSEN
TP1
V18A
RRES
NC
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13 14
48 47 46 45
24
25
26
27
28
17
18
19
20
21
22
23
40 39 38 37
36
35
4142
ISEN2
ISEN1
IRTN1
IRTN2
PWM2
PWM1
NC
15
16
44 43
VCC
33
32
31
30
29
34
GND
SADDR
CHL8266
TOP VIEW
48 Pin
7mmx 7mm
QFN
Figure 2: CHL8266 Package Top View
