LTC1066-1
10
10661fa
APPLICATIONS INFORMATION
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DC PERFORMANCE
The DC performance of the LTC1066-1 is dictated by the
DC characteristics of the input precision op amp.
1. DC input voltages in the vicinity of the filter’s half of the
total power supply are processed with exactly 0dB (or
1V/V) of gain.
2. The typical DC input voltage ranges are equal to:
V
IN
= ±5.8V, V
S
= ±7.5V
V
IN
= ±3.6V, V
S
= ±5V
V
IN
= ±1.4V, V
S
= ±2.5V
With an input DC voltage range of V
IN
= ±5V, (V
S
=
±7.5V), the measured CMRR was 100dB. Figure 1
shows the DC gain linearity of the filter exceeding the
requirements of a 14-bit, 10V full scale system.
3. The filter output DC offset V
OS(OUT)
is measured with the
input grounded and with dual power supplies. The
V
OS(OUT)
is typically ±0.1mV and it is optimized for the
filter connection shown in the test circuit figure. The
filter output offset is equal to:
V
OS(OUT)
= V
OS
(op amp A) –I
BIAS
× R
F
= 0.1mV (Typ)
4. The V
OS(OUT)
temperature drift is typically 7µV/°C
(T
A
> 25°C), and –7µV/°C (T
A
< 25°C).
5. The V
OS(OUT)
temperature drift can be improved by
using an input resistor R
IN
equal to the feedback resis-
tor R
F
, however, the absolute value of V
OS(OUT)
will
increase. For instance, if a 20k resistor is added in series
with pin 3 (see Test Circuit), the output V
OS
drift will be
improved by 2µV/°C to 3µV/°C, however, the V
OS(OUT)
may increase by 1mV
(MAX)
.
6. The filter DC output offset voltage V
OS(OUT)
is indepen-
dent from the filter clock frequency (f
CLK
≤ 250kHz).
Figures 2 and 3 show the V
OS(OUT)
variation for three
different power supplies and for clock frequencies up to
5MHz. Both figures were traced with the LTC1066-1
soldered into the PC board. Power supply decoupling is
very important, especially with ±7.5V supplies. If nec-
essary connect a small resistor (20Ω) between pins 5
and 18, and between pins 10 and 4, to isolate the
precision op amp supply pin from the switched
capacitor network supply (see the Test Circuit).
INPUT VOLTAGE (VDC)
–6 –5 –3 –1 1 3 5
V
IN
– V
OUT
(µV)
75
50
25
0
–25
–50
–75
–100
–125
2
1066-1 F01
–4
–2
0
46
V
S
= ±7.5V
T
A
= 25°C
f
CLK
= 1MHz
f
C
= 20kHz
Figure 1. DC Gain Linearity
CLOCK FREQUENCY (MHz)
0 0.5 1.5 2.5 3.5 4.5
FILTER OUTPUT OFFSET VOLTAGE CHANGE (mV)
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
4.0
1066-1 F03
1.0
2.0
3.0
5.0
V
S
= ±2.5V
V
S
= ±5V
V
S
= ±7.5V
T
A
= 25°C
f
CLK
/f
C
= 50:1
CLOCK FREQUENCY (MHz)
0 0.5 1.5 2.5 3.5 4.5
FILTER OUTPUT OFFSET VOLTAGE CHANGE (mV)
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
4.0
1066-1 F02
1.0
2.0
3.0
5.0
V
S
= ±2.5V
V
S
= ±5V
V
S
= ±7.5V
LINEAR PHASE
T
A
= 25°C
f
CLK
/f
C
= 100:1
Figure 2. Output Offset Change vs Clock
(Relative to Offset for f
CLK
= 250kHz)
Figure 3. Output Offset Change vs Clock
(Relative to Offset for f
CLK
= 250kHz)
