IDT
®
PC MAIN CLOCK - CK540 1247C—06/16/11
Advance Information
9UMS9001
PC MAIN CLOCK - CK540
3
Pin Description (continued)
PIN # PIN NAME TYPE DESCRIPTION
29 CLKREQ0# IN
Clock request input for SRC output pair 0. See the SRC, LCD, DOT Power Management Table for
details
30 SRC0C_LPRS OUT
Complement side of low-power CK505-type SRC0 differential clock. Rs is integrated (No external
series resistor required).
31 SRC0T_LPRS OUT
True side of low-power CK505-type SRC0 differential clock. Rs is integrated (No external series
resistor required).
32 SRC1C_LPRS OUT
Complement side of low-power CK505-type SRC1 differential clock. Rs is integrated (No external
series resistor required).
33 SRC1T_LPRS OUT
True side of low-power CK505-type SRC1 differential clock. Rs is integrated (No external series
resistor required).
34 GNDSRC PWR Ground for SRC clocks
35 VDDIO_SRC PWR Power supply for SRC outputs. VDD_IO = 1.05 to 3.3V +/-5%.
36 SRC2C_LPRS OUT
Complement side of low-power CK505-type SRC2 differential clock. Rs is integrated (No external
series resistor required).
37 SRC2T_LPRS OUT
True side of low-power CK505-type SRC2 differential clock. Rs is integrated (No external series
resistor required).
38 SRC3C_LPRS OUT
Complement side of low-power CK505-type SRC3 differential clock. Rs is integrated (No external
series resistor required).
39 SRC3T_LPRS OUT
True side of low-power CK505-type SRC3 differential clock. Rs is integrated (No external series
resistor required).
40 VDDCORE_3.3 PWR 3.3V Power supply for 3.3V core
41 CLKREQ3# IN
Clock request input for SRC output pair 3. See the SRC, LCD, DOT Power Management Table for
details
42 CLKREQ2# IN
Clock request input for SRC output pair 2. See the SRC, LCD, DOT Power Management Table for
details
43 FSLB IN
Low threshold Frequency Select input. See Table 1: CPU Frequency Select Table and the Vih_fs and
Vil_fs specifications.
44 CPU_STOP# IN Stops all CPU clocks except those set to be free running.
45 CPUITPC_LPRS OUT
Complement side of low-power CK505-type CPUITP differential clock. Rs is integrated (No external
series resistor required). Note that this pin is NOT muxed with an SRC output.
46 CPUITPT_LPRS OUT
True side of low-power CK505-type CPUITP differential clock. Rs is integrated (No external series
resistor required).
47 CPU1C_LPRS OUT
Complement side of low-power CK505-type CPU1 differential clock. Rs is integrated (No external
series resistor required). Note that this pin is NOT muxed with an SRC output.
48 CPU1T_LPRS OUT
True side of low-power CK505-type CPU1 differential clock. Rs is integrated (No external series
resistor required).
49 VDDIO_CPU PWR Power supply for CPU outputs. VDD_IO = 1.05 to 3.3V +/-5%.
50 GNDCPU PWR Ground Pin for CPU Outputs
51 CPU0C_LPRS OUT
Complement side of low-power CK505-type CPU1 differential clock. Rs is integrated (No external
series resistor required). Note that this pin is NOT muxed with an SRC output.
52 CPU0T_LPRS OUT
True side of low-power CK505-type CPU1 differential clock. Rs is integrated (No external series
resistor required).
53 VDDCPUPLL_3.3 PWR 3.3V Power Supply for CPU PLL.
54 CK_PWRGD#/PD IN
Notifies 9UMS9001 to sample latched inputs or enter power down mode.
1 = Power down mode
Falling Edge = Sample latched inputs
0 = Normal operation
55 FSLC IN
Low threshold Frequency Select input. See Table 1: CPU Frequency Select Table and the Vih_fs and
Vil_fs specifications.
56 GNDREF PWR Ground pin for crystal oscillator circuit and REF output