Document Number: 001-63745 Rev. *D Page 22 of 37
AC I
2
C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C T
A
85 C or 3.0 V to 3.6 V and –40 C T
A
85 C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 C
and are for design guidance only.
Figure 8. Definition for Timing for Fast/Standard Mode on the I
2
C Bus
Table 19. AC Characteristics of the I
2
C SDA and SCL Pins
Symbol Description
Standard Mode Fast Mode
Units Notes
Min Max Min Max
F
SCLI2C
SCL clock frequency 0 100
[17]
0400
[17]
kHz
t
HDSTAI2C
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
4.0 –0.6– s
t
LOWI2C
LOW period of the SCL clock 4.7 –1.3– s
t
HIGHI2C
HIGH period of the SCL clock 4.0 –0.6– s
t
SUSTAI2C
Setup time for a repeated START condition 4.7 –0.6– s
t
HDDATI2C
Data hold time 0 –0– s
t
SUDATI2C
Data setup time 250 –100
[18]
–ns
t
SUSTOI2C
Setup time for STOP condition 4.0 –0.6– s
t
BUFI2C
Bus free time between a STOP and START
condition
4.7 –1.3– s
t
SPI2C
Pulse width of spikes are suppressed by the
input filter.
– –050ns
I2C_SDA
I2C_SCL
S
Sr
SP
T
BUFI2C
T
SPI2C
T
SUSTOI2C
T
SUSTAI2C
T
LOWI2C
T
HIGHI2C
T
HDDATI2C
T
HDSTAI2C
T
SUDATI2C
START Condition Repeated START Condition
STOP Condition
Notes
17. F
SCLI2C
is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the
F
SCLI2C
specification adjusts accordingly
18. A Fast-Mode I
2
C-bus device can be used in a Standard-Mode I
2
C-bus system, but the requirement t
SUDATI2C
250 ns must then be met. This is automatically the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line t
rmax
+t
SUDATI2C
= 1000 + 250 = 1250 ns (according to the Standard-Mode I
2
C-bus specification) before the SCL line is released.
