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SP6136EB

P1-P3P4-P6P7-P9
Rev 5/01/06 SP6136 Evaluation Manual Copyright © 2006 Sipex Corporation
Page 4 of 9
Figure 9. Output Noise at No Load Figure 10. Output Noise at 7A Load
Series R Isat Manufacturer
mOhms (A) LxW(mm) Ht.(mm) Website
ESR Ripple Current Voltage Capacitor Manufacturer
ohms (max) (A) @ 45C LxW(mm) Ht.(mm) (V) Type Website
TDK
C3225X5R1C226M
TDK
C3225X5R0J107M
RDS(on) ID Current Voltage Foot Print Manufacturer
ohms (max) (A) nC (Typ) nC (Max) (V) Website
N-Ch VISHAY Si4354DY 18.50 9.0 7.0 10.5
30.0 SO-8 www.vishay.com
N-Ch VISHAY Si4886DY 13.5 11.0 14.5 20.0
30.0 SO-8 www.vishay.com
INDUCTORS - SURFACE MOUNT
Inductance
(uH)
Manufacturer/Part No.
Inductor Specification
Size Inductor Type
2.2
Inter-Technical
SC7232-2R2M
10.4 13.00 7.2x6.6 3.20
Shielded Ferrite Core
www.inter-technical.com
CAPACITORS - SURFACE MOUNT
Capacitance(
uF)
Manufacturer/Part No.
Capacitor Specification
Size
22 0.005 4.00 3X2 2.00
16.0 X5R Ceramic www.TDK.com
100 0.005 4.00 3X2 2.00
6.3 X5R Ceramic www.TDK.com
MOSFETS - SURFACE MOUNT
MOSFET Manufacturer/Part No.
MOSFET Specification
Qg
Table 1: SP6136EB Suggested Components and Vendor Lists
Vout Ripple(10mV/div)
SW Node
Vin=12V
Vout=3.3V
Vout Ripple(10mV/div)
SW Node
Vin=12V
Vout=3.3V
Rev 5/01/06 SP6136 Evaluation Manual Copyright © 2006 Sipex Corporation
Page 5 of 9
LOOP COMPENSATION DESIGN
The open loop gain of the SP6136EB can be divided into the gain of the error amplifier
G
AMP
(
S
),
PWM modulator G
PWM
, buck converter output stage G
OUT
(
S
), and feedback resistor
divider G
FBK
. In order to crossover at the selected frequency fc, the gain of the error amplifier
has to compensate for the attenuation caused by the rest of the loop at this frequency. The
goal of loop compensation is to manipulate the open loop frequency response such that its
gain crosses over 0dB at a slope of –20dB/dec. The open loop crossover frequency should be
higher than the ESR zero of the output capacitors but less than 1/5 of the switching frequency
fs to insure proper operation. Since the SP6136EB is designed with ceramic type output
capacitors, a Type III compensation circuit is required to give a phase boost of 180° in order to
counteract the effects of the output LC under damped resonance double pole frequency.
Figure 11. SP6136EB Voltage Mode Control Loop with Loop Dynamic
Rev 5/01/06 SP6136 Evaluation Manual Copyright © 2006 Sipex Corporation
Page 6 of 9
The simple guidelines for positioning the poles and zeros and for calculating the component
values for Type III compensation are as follows:
KR 1.681
=
8
.
0
18.0
2
−
×
=
Vout
R
R
(sets output voltage)
LC
RZSF
CZ
1
1
1
3
××
= (sets first zero)
(
)
(
)
Vin
Vramp
CZfc
CoutLfc
RZ ×
××
+×××
=
328.6
128.6
2
2
(sets the cross-over frequency, fc)
LC
RZZSF
CZ
1
2
1
2
××
= (sets second zero)
228.6
1
1
RZfs
CP
××
= (sets first high-frequency pole)
328.6
1
3
CZfs
RZ
××
= (sets second high-frequency pole)
Where ZSF=(f compensation double zero)/(f circuit double pole)
Here ZSF is set at 0.8.
As a particular example, consider for the following SP6136EB, 7AMAX with a type III Voltage
Loop Compensation component selections:
Vin = 12V
Vout = 3.30V @ 0 to 7A load
Select L = 2.2 uH => 30% current ripple.
Select Cout = 100uF Ceramic capacitor (Resr ≈ 5mΩ)
fs = 600KHz SP6136ER1 internal Oscillator Frequency
Vramp_pp = 1.0V SP6136ER1 internal Ramp Peak to Peak Amplitude
P1-P3P4-P6P7-P9

SP6136EB

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Power Management IC Development Tools Synchronous Buck Controller
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