25AA080/25LC080/25C080
DS21230E-page 6 1997-2012 Microchip Technology Inc.
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS
after a valid write
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
being initiated.
2.2 Serial Output (SO)
The SO pin is used to transfer data out of the 25XX080.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
2.3 Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
Status register to prohibit writes to the nonvolatile bits
in the Status register. When WP is low and WPEN is
high, writing to the nonvolatile bits in the Status register
is disabled. All other operations function normally.
When WP
is high, all functions, including writes to the
nonvolatile bits in the Status register operate normally.
If the WPEN bit is set, WP
low during a Status register
write sequence will disable writing to the Status
register. If an internal write cycle has already begun,
WP
going low will have no effect on the write.
The WP
pin function is blocked when the WPEN bit in
the Status register is low. This allows the user to install
the 25XX080 in a system with WP
pin grounded and
still be able to write to the Status register. The WP
pin
functions will be enabled when the WPEN bit is set
high.
2.4 Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
2.5 Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25XX080. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
2.6 Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25XX080 while in the middle of a serial sequence
without having to retransmit the entire sequence again.
It must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD
pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to-
low transition. The 25XX080 must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD
must be brought
high while the SCK pin is low, otherwise serial commu-
nication will not resume. Lowering the HOLD line at any
time will tri-state the SO line.
Name PDIP SOIC Function
CS
1 1 Chip Select Input
SO 2 2 Serial Data Output
WP
3 3 Write-Protect Pin
Vss 4 4 Ground
SI 5 5 Serial Data Input
SCK 6 6 Serial Clock Input
HOLD
7 7 Hold Input
Vcc 8 8 Supply Voltage
