AD539
Rev. B | Page 6 of 20
09679-003
V
X
HF COMP
V
Y1
+V
S
W1
Z1
CHAN1 OUTPUT
BASE COMMON
–V
S
V
Y2
INPUT COMMON
BASE COMMON
CHAN2 PUTPUT
Z2
OUTPUT COMMON
W2
AD539
TOP VIEW
(Not to Scale)
1
2
3
4
16
15
14
13
5
6
7
12
11
10
8
9
Figure 3. 16-Lead PDIP and SBDIP Pin Configurations (N-16, D-16)
Table 3. 16-Lead PDIP and SBDIP Pin Function Descriptions
Pin No. Mnemonic Description
1 V
X
Control Channel Input.
2 HF COMP High Frequency Compensation.
3 V
Y1
Channel 1 Input.
4 +V
S
Positive Supply Rail.
5 –V
S
Negative Supply Rail.
6 V
Y2
Channel 2 Input.
7 INPUT COMMON Internal Common Connection for the Input Amplifier Circuitry.
8 OUTPUT COMMON Internal Common Connection for The Output Amplifier Circuitry.
9 W2 6 kΩ Feedback Resistor for Channel 2.
10 Z2 6 kΩ Feedback Resistor for Channel 2.
11 CHAN2 OUTPUT Channel 2 Product of V
X
and V
Y2
.
12 BASE COMMON Increases Negative Output Compliance.
13 BASE COMMON Increases Negative Output Compliance.
14 CHAN1 OUTPUT Channel 1 Product of V
X
and V
Y1
.
15 Z1 6 kΩ Feedback Resistor for Channel 1.
16 W1 6 kΩ Feedback Resistor for Channel 1.
