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AT17N002-10TQC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
4
AT17N256/512/010/002/040
3020C–CNFG–08/07
Block Diagram
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter-
face directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external intelligent controller.
The configuration EEPROM RESET/OE
and CE pins control the tri-state buffer on the
DATA output pin and enable the address counter. When RESET/OE
is driven High, the
configuration EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17N series configurator. If CE is held High after the
RESET/OE
reset pulse, the counter is disabled and the DATA output pin is tri-stated.
When OE
is subsequently driven Low, the counter and the DATA output pin are
enabled. When RESET/OE
is driven High again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of CE
. Upon power-up, the address
counter is automatically reset.
POWER ON
RESET
SER_EN
5
AT17N256/512/010/002/040
3020C–CNFG–08/07
DATA Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
CLK Clock input. Used to increment the internal address and bit counter for reading and
programming.
RESET/OE Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low
level on RESET
/OE resets both the address and bit counters. A High level (with CE
Low) enables the data output driver. The logic polarity of this input is programmable as
either RESET/OE
or RESET/OE. For most applications, RESET should be programmed
active Low. This document describes the pin as RESET
/OE.
CE Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the
address counter and enables the data output driver. A High level on CE
disables both
the address and bit counters and forces the device into a low-power standby mode.
Note that this pin will not enable/disable the device in the Two-Wire Serial Programming
mode (SER_EN
Low).
GND Ground pin. A 0.2 µF decoupling capacitor between V
CC
and GND is recommended.
VCC(SER_EN) Serial enable must be held High during FPGA loading operations. Bringing SER_EN
Low enables the Two-Wire Serial Programming Mode. For non-ISP applications,
SER_EN
should be tied to V
CC
.
V
CC
3.3V (±10%) Commercial and Industrial power supply pin.
NC NC pins are No Connect pins, which are not internally bonded out to the die.
DC DC pins are No Connect pins internally connected to the die. It is not recommended to
connect these pins to any external signal.
Pin Description
Name I/O
AT17N256
AT17N512/
AT17N010
AT17N002
AT17N040
8
DIP/
SOIC
20
SOIC
8
DIP
20
SOIC
20
SOIC
44
TQFP
44
TQFP
DATAI/O111114040
CLKI232334343
RESET/OE
I383881313
CE
I4 10 4 10101515
GND 5 11 5 11111818
DCO6 13 6 13132121
DCO–––––2323
VCC(SER_EN
)I7 18 7 18183535
V
CC
8 20 8 20203838
6
AT17N256/512/010/002/040
3020C–CNFG–08/07
FPGA Master Serial
Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configura-
tion program. The program is loaded either automatically upon power-up, or on
command, depending on the state of the FPGA mode pins. In Master mode, the FPGA
automatically loads the configuration program from an external memory. The AT17N
Serial Configuration EEPROM has been designed for compatibility with the Master
Serial mode.
This document discusses the master serial mode configuration of Atmel AT17N series
configuration memories, pin compatible with Spartan-II, Spartan-IIE and Spartan XL
OTP PROMs.
Control of
Configuration
Most connections between the FPGA device and the AT17N Serial EEPROM are simple
and self-explanatory.
• The DATA output of the AT17N series configurator drives DIN of the FPGA devices.
• The master FPGA CCLK output drives the CLK input of the AT17N series
configurator.
• SER_EN
must be connected to V
CC
(except during ISP).
•The CE
and OE/Reset are driven by the FPGA to enable output data buffer of the
EEPROM.
Programming Mode The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the Two-Wire serial bus. The programming is done at V
CC
supply
only. Programming super voltages are generated inside the chip.
Standby Mode The AT17N series configurators enter a low-power standby mode whenever CE is
asserted High. In this mode, the AT17N256 configurator consumes less than 50 µA of
current at 3.3V (100 µA for the AT17N512/010 and 200 µA for the AT17N002/040).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

AT17N002-10TQC

Mfr. #:
Buy AT17N002-10TQC
Manufacturer:
Microchip Technology / Atmel
Description:
FPGA - Configuration Memory CONFIG SERIAL EEPROM 2M 3V-10MHZ
Lifecycle:
New from this manufacturer.
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