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AD5542CRZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
AD5541/AD5542 Data Sheet
Rev. F | Page 4 of 20
Parameter
Min Typ Max Unit Test Conditions
POWER REQUIREMENTS Digital inputs at rails
V
2.7 5.5 V
I
125 150 μA
Power Dissipation 0.625 0.825 mW
1
Temperature ranges are as follows: A, B, C versions: −40°C to +85°C; J, L versions: 0°C to 70°C.
2
Reference input resistance is code-dependent, minimum at 0x8555.
3
Guaranteed by design, not subject to production test.
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V ±10%, V
REF
= 2.5 V, V
INH
= 3 V and 90% of V
DD
, V
INL
= 0 V and 10% of V
DD
, AGND = DGND = 0 V; −40°C < T
A
<
+85°C, unless otherwise noted.
Table 3.
Parameter
1, 2
Limit
Unit Description
f
SCLK
25
MHz max
SCLK cycle frequency
t
1
40 ns min SCLK cycle time
t
2
20 ns min SCLK high time
t
3
20 ns min SCLK low time
t
4
10 ns min
CS
low to SCLK high setup
t
5
15 ns min
CS
high to SCLK high setup
t
6
30 ns min SCLK high to
CS
low hold time
t
7
20 ns min SCLK high to
CS
high hold time
t
8
15 ns min Data setup time
t
9
4 ns min Data hold time (V
INH
= 90% of V
DD
, V
INL
= 10% of V
DD
)
t
9
7.5 ns min Data hold time (V
INH
= 3V, V
INL
= 0 V)
t
10
30
ns min
LDAC
pulse width
t
11
30 ns min
CS
high to
LDAC
low setup
t
12
30 ns min
CS
high time between active periods
1
Guaranteed by design and characterization. Not production tested
2
All input signals are specified with t
R
= t
F
= 1 ns/V and timed from a voltage level of (V
INL
+ V
INH
)/2.
SCLK
CS
DIN
DB15
LDAC*
t
6
t
4
t
12
t
8
t
5
t
2
t
3
t
1
t
7
t
5
t
11
t
10
*AD5542 ONLY. CAN BE TIED PERMANENTLY LOW IF REQUIRED.
07557-003
Figure 3. Timing Diagram
Data Sheet AD5541/AD5542
Rev. F | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 4.
Parameter Rating
V
DD
to AGND −0.3 V to +6 V
Digital Input Voltage to DGND −0.3 V to V
DD
+ 0.3 V
V
OUT
to AGND −0.3 V to V
DD
+ 0.3 V
AGND, AGNDF, AGNDS to DGND −0.3 V to +0.3 V
Input Current to Any Pin Except Supplies ±10 mA
Operating Temperature Range
Industrial (A, B, C Versions)
−40°C to +85°C
Commercial (J, L Versions) 0°C to 70°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature (T
J
max) 150°C
Package Power Dissipation (T
J
max – T
A
)/θ
JA
Thermal Impedance, θ
JA
SOIC (R-8) 149.5°C/W
SOIC (R-14) 104.5°C/W
Lead Temperature, Soldering
Peak Temperature
1
260°C
ESD
2
5 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
1
As per JEDEC Standard 20.
2
HBM Classification
.
AD5541/AD5542 Data Sheet
Rev. F | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
OUT
1
AGND
2
REF
3
CS
4
V
DD
8
DGND
7
DIN
6
SCLK
5
AD5541
TOP VIEW
(Not to Scale)
07557-004
Figure 4. AD5541 Pin Configuration
Table 5. AD5541 Pin Function Descriptions
Pin No. Mnemonic Description
1 V
OUT
Analog Output Voltage from the DAC.
2 AGND Ground Reference Point for Analog Circuitry.
3 REF Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V
DD
.
4
CS
Logic Input Signal. The chip select signal is used to frame the serial data input.
5 SCLK Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%.
6 DIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK.
7
DGND
Digital Ground. Ground reference for digital circuitry.
8 V
DD
Analog Supply Voltage, 5 V ± 10%.
07557-005
RFB
1
V
OUT
2
AGNDF
3
AGNDS
4
V
DD
14
INV
13
DGND
12
LDAC
11
REFS
5
DIN
10
REFF
6
NC
9
CS
7
SCLK
8
NC = NO CONNECT
AD5542
TOP VIEW
(Not to Scale)
Figure 5. AD5542 Pin Configuration
Table 6. AD5542 Pin Function Descriptions
Pin No. Mnemonic Description
1 RFB Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output.
2 V
OUT
Analog Output Voltage from the DAC.
3
AGNDF
Ground Reference Point for Analog Circuitry (Force).
4 AGNDS Ground Reference Point for Analog Circuitry (Sense).
5 REFS Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V
DD
.
6 REFF Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V
DD
.
7
CS
Logic Input Signal. The chip select signal is used to frame the serial data input.
8 SCLK Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%.
9 NC No Connect.
10 DIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK.
11
LDAC
LDAC
Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the
input register.
12 DGND Digital Ground. Ground reference for digital circuitry.
13
INV
Connected to the Internal Scaling Resistors of the DAC. Connect the INV pin to external op amps inverting input in
bipolar mode.
14 V
DD
Analog Supply Voltage, 5 V ± 10%.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

AD5542CRZ-REEL7

Mfr. #:
Buy AD5542CRZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 16-Bit DAC BiPolar V-Out
Lifecycle:
New from this manufacturer.
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