AD5542CRZ Datasheet AD5541ARZ, AD5541CRZ, AD5541BRZ | P10-P12

AD5541/AD5542 Data Sheet

Rev. F | Page 10 of 20

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, relative accuracy or INL is a measure of the

maximum deviation, in LSBs, from a straight line passing

through the endpoints of the DAC transfer function. A typical

INL vs. code plot can be seen in Figure 6.

Differential Nonlinearity (DNL)

DNL is the difference between the measured change and the

ideal 1 LSB change between any two adjacent codes. A specified

differential nonlinearity of ±1 LSB maximum ensures mono-

tonicity. Figure 9 illustrates a typical DNL vs. code plot.

Gain Error

Gain error is the difference between the actual and ideal analog

output range, expressed as a percent of the full-scale range.

It is the deviation in slope of the DAC transfer characteristic

from ideal.

Gain Error Temperature Coefficient

Gain error temperature coefficient is a measure of the change

in gain error with changes in temperature. It is expressed in

ppm/°C.

Zero Code Error

Zero code error is a measure of the output error when zero code

is loaded to the DAC register.

Zero Code Temperature Coefficient

This is a measure of the change in zero code error with a change

in temperature. It is expressed in mV/°C.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nV-sec

and is measured when the digital input code is changed by

1 LSB at the major carry transition. A plot of the digital-to-

analog glitch impulse is shown in Figure 19.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into

the analog output of the DAC from the digital inputs of the

DAC, but it is measured when the DAC output is not updated.

is held high while the CLK and DIN signals are toggled. It

is specified in nV-sec and is measured with a full-scale code

change on the data bus, that is, from all 0s to all 1s and vice

versa. A typical plot of digital feedthrough is shown in

Figure 18.

Power Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the DAC is affected by changes

in the power supply voltage. Power-supply rejection ratio is

quoted in terms of percent change in output per percent change

in V

for full-scale output of the DAC. V

is varied by ±10%.

Reference Feedthrough

Reference feedthrough is a measure of the feedthrough from the

REF

input to the DAC output when the DAC is loaded with all

0s. A 100 kHz, 1 V p-p is applied to V

REF

. Reference feedthrough

is expressed in mV p-p.

Data Sheet AD5541/AD5542

Rev. F | Page 11 of 20

THEORY OF OPERATION

The AD5541/AD5542 are single, 16-bit, serial input, voltage

output DACs. They operate from a single supply ranging from

2.7 V to 5.5 V and consume typically 125 µA with a supply of

5 V. Data is written to these devices in a 16-bit word format,

via a 3- or 4-wire serial interface. To ensure a known power-up

state, these parts are designed with a power-on reset function.

In unipolar mode, the output is reset to 0 V; in bipolar mode,

the AD5542 output is set to −V

REF

. Kelvin sense connections for

the reference and analog ground are included on the AD5542.

DIGITAL-TO-ANALOG SECTION

The DAC architecture consists of two matched DAC sections.

A simplified circuit diagram is shown in Figure 22. The DAC

architecture of the AD5541/AD5542 is segmented. The four

MSBs of the 16-bit data-word are decoded to drive 15 switches,

E1 to E15. Each switch connects one of 15 matched resistors to

either AGND or V

REF

. The remaining 12 bits of the data-word

drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder

network.

2R . . . . .

S1 . . . . .

2R . . . . .

E2 . . . . .

2R 2R

E15

R R

REF

OUT

12-BIT R-2R LADDER

FOUR MSBs DECODED

INTO 15 EQUAL SEGMENTS

07557-022

Figure 22. DAC Architecture

With this type of DAC configuration, the output impedance

is independent of code, while the input impedance seen by

the reference is heavily code dependent. The output voltage is

dependent on the reference voltage, as shown in the following

equation:

REF

OUT

where:

D is the decimal data-word loaded to the DAC register.

N is the resolution of the DAC.

For a reference of 2.5 V, the equation simplifies to the following:

536,65

5.2 D

OUT

This gives a V

OUT

of 1.25 V with midscale loaded and 2.5 V with

full-scale loaded to the DAC.

The LSB size is V

REF

/65,536.

SERIAL INTERFACE

The AD5541/AD5542 are controlled by a versatile 3- or 4-wire

serial interface that operates at clock rates up to 25 MHz and is

compatible with SPI, QSPI, MICROWIRE, and DSP interface

standards. The timing diagram is shown in Figure 3. Input data

is framed by the chip select input,

. After a high-to-low

transition on

, data is shifted synchronously and latched into

the input register on the rising edge of the serial clock, SCLK.

Data is loaded MSB first in 16-bit words. After 16 data bits have

been loaded into the serial input register, a low-to-high transition

transfers the contents of the shift register to the DAC. Data

can be loaded to the part only while

is low.

The AD5542 has an

LDAC

function that allows the DAC latch

to be updated asynchronously by bringing

LDAC

low after

goes high.

LDAC

should be maintained high while data is written

to the shift register. Alternatively,

LDAC

can be tied perma-

nently low to update the DAC synchronously. With

LDAC

tied

permanently low, the rising edge of

loads the data to the DAC.

UNIPOLAR OUTPUT OPERATION

These DACs are capable of driving unbuffered loads of 60 kΩ.

Unbuffered operation results in low supply current, typically

300 μA, and a low offset error. The AD5541 provides a unipolar

output swing ranging from 0 V to V

REF

. The AD5542 can be

configured to output both unipolar and bipolar voltages. Figure 23

shows a typical unipolar output voltage circuit. The code table

for this mode of operation is shown in Table 7.

07557-023

OUT

REFS*REF(REFF*)

DGND AGND

DIN

SCLK

LDAC*

AD5541/AD5542

AD820/

OP196

0.1µF0.1µF

10µF

UNIPOLAR

OUTPUT

EXTERNAL

P AMP

2.5V

SERIAL

INTERFACE

*AD5542 ONLY.

Figure 23. Unipolar Output

Table 7. Unipolar Code Table

DAC Latch Contents

MSB LSB Analog Output

1111 1111 1111 1111 V

REF

× (65,535/65,536)

1000 0000 0000 0000 V

REF

× (32,768/65,536) = ½ V

REF

0000 0000 0000 0001 V

REF

× (1/65,536)

0000 0000 0000 0000 0 V

AD5541/AD5542 Data Sheet

Rev. F | Page 12 of 20

Assuming a perfect reference, the unipolar worst-case output

voltage can be calculated from the following equation:

OUT-UNI

( )

INLVVV

ZSE

REF

+++×=

where:

OUT−UNI

is unipolar mode worst-case output.

D is code loaded to DAC.

REF

is reference voltage applied to the part.

is gain error in volts.

ZSE

is zero scale error in volts.

INL is integral nonlinearity in volts.

BIPOLAR OUTPUT OPERATION

With the aid of an external op amp, the AD5542 can be confi-

gured to provide a bipolar voltage output. A typical circuit of

such operation is shown in Figure 24. The matched bipolar

offset resistors, R

and R

INV

, are connected to an external op

amp to achieve this bipolar output swing, typically R

= R

INV

28 kΩ. Table 8 shows the transfer function for this output

operating mode. Also provided on the AD5542 are a set of

Kelvin connections to the analog ground inputs.

07557-024

OUT

REFSREFF

INV

DGND AGNDF

DIN

SCLK

LDAC

AD5541/AD5542

AGNDS

0.1µF0.1µF

10µF

UNIPOLAR

OUTPUT

EXTERNAL

OP AMP

+2.5V

+5V

–5V

SERIAL

INTERFACE

RFB

Figure 24. Bipolar Output (AD5542 Only)

Table 8. Bipolar Code Table

DAC Latch Contents

MSB LSB Analog Output

1111 1111 1111 1111 +V

REF

× (32,767/32,768)

1000 0000 0000 0001 +V

REF

× (1/32,768)

1000 0000 0000 0000 0 V

0111 1111 1111 1111 −V

REF

× (1/32,768)

0000 0000 0000 0000 −V

REF

× (32,768/32,768) = −V

REF

Assuming a perfect reference, the worst-case bipolar output

voltage can be calculated from the following equation:

OUT-BIP

( )

( ) ( )

[ ]

( )

RDVRDVV

REF

UNIOUT

+−++

−

where:

OUT-BIP

is the bipolar mode worst-case output.

OUT−UNI

is the unipolar mode worst-case output.

is the external op amp input offset voltage.

RD is the R

and R

INV

resistor matching error.

A is the op amp open-loop gain.

OUTPUT AMPLIFIER SELECTION

For bipolar mode, a precision amplifier should be used and

supplied from a dual power supply. This provides the ±V

REF

output. In a single-supply application, selection of a suitable op

amp may be more difficult as the output swing of the amplifier

does not usually include the negative rail, in this case, AGND.

This can result in some degradation of the specified performance

unless the application does not use codes near zero.

The selected op amp needs to have a very low-offset voltage (the

DAC LSB is 38 μV with a 2.5 V reference) to eliminate the need

for output offset trims. Input bias current should also be very

low because the bias current, multiplied by the DAC output

impedance (approximately 6 kΩ), adds to the zero code error.

Rail-to-rail input and output performance is required. For fast

settling, the slew rate of the op amp should not impede the

settling time of the DAC. Output impedance of the DAC is

constant and code-independent, but to minimize gain errors,

the input impedance of the output amplifier should be as high

as possible. The amplifier should also have a 3 dB bandwidth of

1 MHz or greater. The amplifier adds another time constant to

the system, hence increasing the settling time of the output. A

higher 3 dB amplifier bandwidth results in a shorter effective

settling time of the combined DAC and amplifier.

FORCE SENSE AMPLIFIER SELECTION

Use single-supply, low-noise amplifiers. A low-output impedance

at high frequencies is preferred because the amplifiers need to

be able to handle dynamic currents of up to ±20 mA.

REFERENCE AND GROUND

Because the input impedance is code-dependent, the reference

pin should be driven from a low impedance source. The AD5541/

AD5542 operate with a voltage reference ranging from 2 V to

. References below 2 V result in reduced accuracy. The full-

scale output voltage of the DAC is determined by the reference.

Table 7 and Table 8 outline the analog output voltage or partic-

ular digital codes. For optimum performance, Kelvin sense

connections are provided on the AD5542.

If the application does not require separate force and sense

lines, tie the lines close to the package to minimize voltage

drops between the package leads and the internal die.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

AD5542CRZ

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Digital to Analog Converters - DAC IC 16-Bit BiPolar V-Out

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AD5542CRZ

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