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CRD-001

P1-P3P4-P6
1
Subject to change without notice.
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SiC MOSFET Isolated Gate Driver
SiC MOSFET Isolated Gate Driver
CPWR-AN10, REV -C
SiC MOSFET Isolated Gate Driver
This article describes an implementation of an isolated gate driver suitable for testing and
evaluating SiC MOSFETs in a variety of applications. This design replaces previous versions of
this application note and include new enhancements. The enhancements are as follows:
• Thecircuitboardhasbeenextendedsothatnow2wattaswellas1watt
DC-DC converters can be used. This enables driving larger MOSFETs or driving
of smaller MOSFETs at higher frequency.
• Thecreep/strikeclearancehasbeensignicantlyincreased.
• Aseparateregulatorhasbeenaddedfortheopto-isolator.Thisallowssimpler
bypassing of the DC-DC converters when non-isolated operation is desired.
• Theoutputresistornetworkhasbeenmodiedwithanadditionaldiodeto
allow separate optimization of turn-on and turn-off transitions.
The top and bottom view of the enhanced gate driver is shown in Figures 1 and 2. The
enhanced creep distance is accomplished with the groove in the printed circuit card. Some
ofthecomponentsarenotpopulatedbecauseoftheaddedexibilityinsettinguptheoutput
network.
The new schematic for the enhanced gate driver is shown in Figure 3. The circuit consists of
twoisolatedDC-DCconverters(X2andX3),anopto-isolator(U1)andthegatedriverinte-
gratedcircuit(U2).Thisintegratedcircuit,theClare/IXYSIXDN609SIcanprovide35Voutput
swingandup to9Aofcurrentwithatypicaloutputresistanceof0.8Ω.Theopto-isolator,
theAvagoACPL-4800-300E,hashighcommonmodetransientimmunity(30kV/µsec)andcan
operatefrom4.5to20V.Aprovisionforaninputlteringcapacitor(C4)hasbeenincluded
if needed. Power is provided by isolated DC-DC converters; one for the positive bias and the
otherfornegativebias.X2andX3arebothfromtheRecomRPseriesof1wattunregulated
isolatedDC-DCconvertersortheRecom[1]RxxP2xxseriesof2wattDC-DCconverters.Ei-
ther type can be accommodated depending on the application.
Figure 1: Isolated Gate Driver Top View Figure 2: Isolated Gate Driver Bottom View
2
CPWR-AN10, REV -C
SiC MOSFET Isolated Gate Driver
This document is provided for informational purposes only and is not a warranty or a specication.
For product specications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at PowerSales@cree.com.
Figure 3: Isolated Gate Driver Schematic
Theseconvertersareinexpensivewithanisolationvoltageratingof5.2kVandalsohaveverylow
isolationcapacitance.Inthisparticularconguration,X2isa12Vin5VoutconverterandX3is
a12Vin,+/-12Voutconverter.Asshownintheschematic,theoutputsoftheconvertersare
series connected and the common connection is referenced to the source terminal. Therefore, VCC
determines the gate pulse positive voltage and –VEE determines the negative gate pulse voltage. The
–VEE node is used as the ground reference for opto-isolator and the gate driver. The opto-isolator’s
maximumoperatingvoltageis20VwhichcanbegreaterthanthevoltageappearingatVCC.An
emitter follower clam consisting of Q1 and D1 has been added to limit the voltage to the opto-isolator
to17.3Vnominal.Abaseresistor(R16)wasincludedifadditionaldampeningisdesiredforthe
emitterfollower.Inpractice,azeroohmresistorworksne.ResistorsR2,R4,R5,R9-R15anddiode
D2canbepopulatedtoprovideoptimumturn-onandturn-offperformance.Inthiscase,onlyR2,R4
andR5arepopulatedwith20ohm1/3wattresistors.Tominimizestrayinductance,capacitorsC8-
C10 are located very close to the source output pin and the gate driver to provide very tight coupling
between the source output terminal and the –VEE node.
THESE COMPONENTS ARE LOCATED ON THE -VEE PLANE
0.100" ISOLATION
BOUNDRY SLIT
BOARD IF REQ.
VCC HIGH
INPUT HIGH
VCC HIGH RTN
INPUT LOW
VCC LOW
VCC LOW RTN
U2
IXDN609SI
VCC
1
IN
2
NC
3
GND
4
VCC
8
OUT
7
OUT
6
GND
5
R4 20 1210
J2
HEADER 6
1
2
3
4
5
6
R5 20 1210
C2
1U
0603
C7
4.7U
1206
U1
ACPL-4800-300E
NC
1
ANODE
2
C ATH
3
NC
4
VCC
8
NC
7
VO
6
GND
5
C10
10U 1210
R6 620
0805
C3
1U
0603
C6
100N
0805
R3 620
0805
R7
47K
0603
C4
TBD
0805
R14
20
R10 20 1210
C8
10N 1210
R8
47K
0603
X2
RP-1205S
+VI N
1
-VIN
2
-VOUT
5
+VOUT
7
Q1
DXT2222A
R12
20
D2
DIODE
R1
10K
0805
JP1
HEADER 3
7
8
9
C5
100N
0805
X3
RP-1212D
+VI N
1
-VIN
2
-VOUT
5
COM
6
+VOUT
7
R2 20 1210
R15
20
JP2
HEADER 3
10
11
12
C9
100N
R9 20 1210
C1
1U
0603
R11 20 1210
D1
MMSZ5248B-7-F
R13
20
VCC LOW
INPUT LOW
INPUT HIGH
VCC LOW RTN
VCC HIGH
SOURCE
GATE
+VC C
VCC HIGH RTN
-VEE
-VEE
-VEE
-VEE
-VEE
-VEE
SOURCE
-VEE
+VC C
SOURCE -VEE
+VC C
-VEE
-VEE
R16 0
0805
Operationofthegatedriverisasfollows.A+10to+12Vpulseisappliedtotheoptocausesthe
gateterminaltogohigh.Theintentofthiscircuitistoaffordthemaximumexibility.Therefore,
unregulated DC-DC converters were used so that the output gate pulse positive and negative voltage
levels can be adjusted at ground level. The gate voltage positive level is adjusted by varying the
voltage between the VCC HIGH and VCC HIGH RTN and the negative pulse level is adjusted by varying
the voltage between the VCC LOW and VCC LOW RTN pins. The procedure is to observe the output
of the gate driver board with an oscilloscope and adjust VCC HIGH and VCC LOW input voltages until
thegatepulseissettothedesiredvalues.Caremustbetakenduringadjustmenttoinsurethatthe
voltagebetweentheVCCand–VEEnodesdoesnotexceedthemaximumratingsofU2,whichis35V.
3
CPWR-AN10, REV -C
SiC MOSFET Isolated Gate Driver
This document is provided for informational purposes only and is not a warranty or a specication.
For product specications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at PowerSales@cree.com.
Figure 4: Non-Isolated Conguration Schematic
R9
ThecircuitcanbemodiedtoremovetheisolatedDC-DCconverterstoallowdirectconnectionof
VCC,source,and–VEEdirectlytoexternalpowersupplies.Thisisaccomplishedbyremovingthe
converters and replacing them with jumper wires. The schematic of this change is shown in Figure 4.
NoticethatX2andX3havebeenremovedandreplacedbyjumpersshownasthedarkbluenets.Also
note,thegatedrivercanalsobeconguredfornonegativegatebiasbynotpopulatingthenegative
gatebiasDC/DCconverterasshowninFigure5.NoticethatDC-DCconverterX3isnotpopulatedand
ajumperisplacedasshowninthedarkbluenet.
Non-regulated DC-DC converters are used in this design to allow convenient adjustment of the high
and low gate pulse amplitudes at ground level. The VCC high input sets the high level and the VCC
low input sets the low level. The procedure is to observe the output of the gate driver board with an
oscilloscope and adjust VCC high and VCC low until the output pulse high and low levels are set to the
desired values.
NC
THESE COMPONENTS ARE LOCATED ON THE -VEE PLANE
0.100" ISOLATION
BOUNDRY SLIT
BOARD IF REQ.
VCC HIGH
VCC HIGH RTN
INPUT HIGH
INPUT LOW
VCC LOW
VCC LO W R TN
U2
IXDN609SI
VCC
1
IN
2
NC
3
GND
4
VCC
8
OU T
7
OU T
6
GND
5
R4 20 1210
J2
HEADER 6
1
2
3
4
5
6
R5 20 1210
C2
1U
0603
C7
4.7U
1206
U1
ACPL-4800-300E
NC
1
ANODE
2
C ATH
3
NC
4
VCC
8
NC
7
VO
6
GND
5
C10
10U 1210
R6 620
0805
C3
1U
0603
C6
100N
0805
R3 620
0805
R7
47K
0603
C4
TBD
0805
R14
20
R10 20 1210
C8
10N 1210
R8
47K
0603
Q1
DXT2222A
R12
20
D2
DIODE
R1
10K
0805
JP1
HEADER 3
7
8
9
C5
100N
0805
R2 20 1210
R15
20
JP2
HEADER 3
10
11
12
C9
100N
R9 20 1210
C1
1U
0603
R11 20 1210
D1
MMSZ5248B-7-F
VCC LOW
R13
20
INPUT LOW
INPUT HIGH
VCC LOW RTN
SOURCE
GATE
+VC C
VCC HIGH RTN
VCC HIGH
-VEE
-VEE
-VEE
-VEE
-VEE
-VEE
SOURCE
-VEE
+VC C
SOURCE -VEE
+VC C
-VEE
-VEE
R16 0
0805
P1-P3P4-P6

CRD-001

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Buy CRD-001
Manufacturer:
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Description:
Power Management IC Development Tools Gate Driver Evaluation Board
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