(Preliminary) PL585-XX
19MHz to 800MHz Low Phase-Noise VCXO
Micrel Inc. • 2180 Fortune Drive • San Jos e, CA 95131 • USA • tel +1(408) 944 -0800 • f ax +1(408) 474-1000 • ww w.micr el.com Rev 11/18/11 Page 6
7. LVPECL OUTPUTS (Q, QB)
Q, QB
Standard LVPECL Termination,
V
DD
= 3.3V
20% - 80% of output waveform
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this
equals ringing!
- Long trace = Transmission Line. Without proper
termination this will cause reflections (looks like
ringing).
- Design long traces (<1 inch) as “striplines” or
“microstrips” with defined impedance.
- Match trace at one side to avoid reflections
bouncing back and forth.
Decoupling and Power Supply Considerations
- Place decoupling capacitors as close as possible to
the V
DD
pin(s) to limit noise from the power supply
- Multiple V
DD
pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with V
DD
can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency
dependant. Typical values to use are 0.1 F for
designs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz .
OUT
OUT
50?
50?
LVPECL Levels Test Circuit
LVPECL Transistion Time Waveform
OUT
OUT
20%
80%
t
R
t
F
VDD
DUTY CYCLE
45 - 55% 55 - 45%
2.0V
50%
