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SY10EL34ZC

P1-P3P4-P4
The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock
generation chips designed explicitly for low skew clock
generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The devices can be driven
by either a differential or single-ended ECL or, if positive
power supplies are used, PECL input signal. In addition,
by using the V
BB output, a sinusoidal source can be AC-
coupled into the device. If a single-ended input is to be
used, the VBB output should be connected to the CLK
input and bypassed to ground via a 0.01µF capacitor.
The VBB output is designed to act as the switching
reference for the input of the EL34/L under single-ended
input conditions. As a result, this pin can only source/
sink up to 0.5mA of current.
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the divider stages. The
internal enable flip-flop is clocked on the falling edge of
the input clock, therefore, all associated specification
limits are referenced to the negative edge of the clock
input.
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple EL34/Ls in a system.
Pin Function
CLK Differential Clock Inputs
EN Synchronous Enable
MR Master Reset
VBB Reference Output
Q0 Differential ÷2 Outputs
Q1 Differential ÷4 Outputs
Q
2 Differential ÷8 Outputs
DESCRIPTION
PIN NAMES
FEATURES
Rev.: F Amendment: /0
Issue Date: August, 1998
5V/3.3V ÷2, ÷4, ÷8 CLOCK
GENERATION CHIP
ClockWorks™
SY10EL34/L
SY100EL34/L
FINAL
PIN CONFIGURATION/BLOCK DIAGRAM
SOIC
TOP VIEW
■ 3.3V and 5V power supply options
■ 50ps output-to-output skew
■ Synchronous enable/disable
■ Master Reset for synchronization
■ Internal 75K
Ω input pull-down resistors
■ Available in 16-pin SOIC package
VCC
EN
NC
CLK
CLK
V
BB
MR
V
EE
Q0
Q0
VCC
Q1
Q1
VCC
Q2
Q2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
R
Q
÷2
Q
R
÷4
Q
÷8
R
Q D
R
1
2
ClockWorks™
SY10EL34/L
SY100EL34/L
Micrel
T
A = –40°CTA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
I
EE Power Supply 10EL — — 49 — — 49 — — 49 — — 49 mA
Current 100EL — — 49 — — 49 — — 49 — — 54
V
BB Output Reference 10EL –1.43 — –1.30 –1.38 — –1.27 –1.35 — –1.25 –1.31 — –1.19 V
Voltage 100EL –1.38 — –1.26 –1.38 — –1.26 –1.38 — –1.26 –1.38 — –1.26
I
IH Input High Current — — 150 — — 150 — — 150 — — 150 µA
DC ELECTRICAL CHARACTERISTICS
(1)
VEE = VEE (Min.) to VEE (Max.); VCC = GND
NOTE:
1. Parametric values specified at: 5 volt Power Supply Range 100EL34 Series: -4.2V to -5.5V.
10EL34 Series -4.75V to -5.5V.
3 volt Power Supply Range 10/100EL34L Series: -3.0V to -3.8V.
TA = –40°CTA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
t
PLH Propagation Delay to ps
tPHL Output CLK 960 1100 1200 960 1100 1200 960 1100 1200 960 1100 1200
MR 650 800 1010 650 800 1010 650 800 1010 650 800 1010
tskew Within-Device Skew
(2)
— — 50 — — 50 — — 50 — — 50 ps
tS Set-up Time EN 400 — — 400 — — 400 — — 400 — — ps
tH Hold Time EN 200 — — 200 — — 200 — — 200 — — ps
VPP Minimum Input Swing
(3)
250 — — 250 — — 250 — — 250 — — mV
VCMR Common Mode Range
(4)
–1.3 — –0.4 –1.4 — –0.4 –1.4 — –0.4 –1.4 — –0.4 V
t
r Output Rise/Fall Times 275 400 525 275 400 525 275 400 525 275 400 525 ps
tf Q (20% – 80%)
VEE = VEE (Min.) to VEE (Max.); VCC = GND
AC ELECTRICAL CHARACTERISTICS
(1)
NOTES:
1. Parametric values specified at: 5 volt Power Supply Range 100EL34 Series: -4.2V to -5.5V.
10EL34 Series -4.75V to -5.5V.
3 volt Power Supply Range 10/100EL34L Series: -3.0V to -3.8V.
2. Skew is measured between outputs under identical transitions.
3. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV.
4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified
range and the peak-to-peak voltage lies between VPP min. and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table
assume a nominal VEE = –3.3V. Note for PECL operation, the VCMR (min) will be fixed at 3.3V – IVCMR (min)I.
TRUTH TABLE
CLK EN MR Function
Z L L Divide
ZZ H L Hold Q0–2
X X H Reset Q0–2
NOTE:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
3
ClockWorks™
SY10EL34/L
SY100EL34/L
Micrel
Ordering Package Operating V
EE Range
Code Type Range (V)
SY10EL34LZC Z16-2 Commercial -3.0 to -3.8
SY10EL34LZCTR Z16-2 Commercial -3.0 to -3.8
SY100EL34LZC Z16-2 Commercial -3.0 to -3.8
SY100EL34LZCTR Z16-2 Commercial -3.0 to -3.8
TIMING DIAGRAM
The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers
will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs
will transition to their next states in the same manner, time and relationship as they would have had the EN signal not been asserted.
PRODUCT ORDERING CODE
Ordering Package Operating VEE Range
Code Type Range (V)
SY10EL34ZC Z16-2 Commercial -4.75 to -5.5
SY10EL34ZCTR Z16-2 Commercial -4.75 to -5.5
SY100EL34ZC Z16-2 Commercial -4.2 to -5.5
SY100EL34ZCTR Z16-2 Commercial -4.2 to -5.5
3.3V
5V
EN
Q1
Q2
CLK
Internal Clock
Disabled
Internal Clock
Enabled
Q0
P1-P3P4-P4

SY10EL34ZC

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Description:
IC CLK GEN /2/4/6 5V/3.3V 16SOIC
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