HEF40193B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 18 November 2011 4 of 19
NXP Semiconductors
HEF40193B
4-bit up/down binary counter
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 3. Pin configuration
HEF40193B
D1 V
DD
Q1 D0
Q0 MR
CPD TCD
CPU TCU
Q2 PL
Q3 D2
V
SS
D3
001aae581
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
D0 to D3 15, 1, 10, 9 parallel data input
CPU 5 count-up clock pulse input (LOW-to-HIGH, edge-triggered)
CPD 4 count-down clock pulse input (LOW-to-HIGH, edge-triggered)
PL
11 parallel load input (active LOW)
MR 14 master reset input (asynchronous)
Q0 to Q3 3, 2, 6, 7 buffered counter output
TCU
12 buffered terminal count-up (carry) output (active LOW)
TCD
13 buffered terminal count-down (borrow) output (active LOW)
V
DD
16 supply voltage
V
SS
8 ground supply voltage
HEF40193B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 18 November 2011 5 of 19
NXP Semiconductors
HEF40193B
4-bit up/down binary counter
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; = positive-going transition.
Table 3. Function table
[1]
MR PL CPU CPD Mode
HXXXreset (asynchronous)
L L X X parallel load
LH H count-up
LHH count-down
Fig 4. Timing diagram
001aae586
015012141310151413
PL
MR
D0
D1
D2
D3
CPU
CPD
Q0
Q1
Q2
Q3
TCU
TCD
COUNT
HEF40193B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 18 November 2011 6 of 19
NXP Semiconductors
HEF40193B
4-bit up/down binary counter
7. Limiting values
[1] For DIP16 package: P
tot
derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: P
tot
derates linearly with 8 mW/K above 70 C.
8. Recommended operating conditions
Logic equations for terminal count:
Fig 5. State diagram
001aae584
0
15
14
13
12
count up
count down
1 2 3 4
5
6
7
11 10 9 8
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 +18 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
DD
+ 0.5 V - 10 mA
V
I
input voltage 0.5 V
DD
+ 0.5 V
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
DD
+ 0.5 V - 10 mA
I
I/O
input/output current - 10 mA
I
DD
supply current - 50 mA
T
stg
storage temperature 65 +150 C
T
amb
ambient temperature 40 +85 C
P
tot
total power dissipation DIP16 package
[1]
-750mW
SO16 package
[2]
-500mW
P power dissipation per output - 100 mW
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
DD
supply voltage 3 - 15 V
V
I
input voltage 0 - V
DD
V
T
amb
ambient temperature in free air 40 - +85 C

HEF40193BP,652

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Counter ICs 4-BIT U/D BIN COUNTR
Lifecycle:
New from this manufacturer.
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