HEF40193B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 18 November 2011 10 of 19
NXP Semiconductors
HEF40193B
4-bit up/down binary counter
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
t
su
set-up time Dn to PL;
see Figure 6
5 V 160 80 - ns
10 V 6030- ns
15 V 5025- ns
t
h
hold time Dn to PL;
see Figure 6
5 V +10 70 - ns
10 V +5 25 - ns
15 V +5 20 - ns
Table 7. Dynamic characteristics
…continued
V
SS
= 0 V; T
amb
= 25
C; for test circuit see Figure 7; unless otherwise specified.
Symbol Parameter Conditions V
DD
Extrapolation formula
[1]
Min Typ Max Unit
Table 8. Dynamic power dissipation P
D
P
D
can be calculated from the formulas shown. V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol Parameter V
DD
Typical formula for P
D
(W) where:
P
D
dynamic power dissipation 5 V P
D
= 600 f
i
+ (f
o
C
L
) V
DD
2
f
i
= input frequency in MHz,
f
o
= output frequency in MHz,
C
L
= output load capacitance in pF,
V
DD
= supply voltage in V,
(f
o
C
L
) = sum of the outputs.
10 V P
D
= 2700 f
i
+ (f
o
C
L
) V
DD
2
15 V P
D
= 7500 f
i
+ (f
o
C
L
) V
DD
2
