RT8011/A
13
DS8011/A-02 March 2011 www.richtek.com
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as :
Efficiency = 100% (L1+ L2+ L3+ ...) where L1, L2, etc.
are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: V
DD
quiescent current and I
2
R losses.
The V
DD
quiescent current loss dominates the efficiency
loss at very low load currents whereas the I
2
R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve
at very low load currents can be misleading since the
actual power lost is of no consequence.
1. The V
DD
quiescent current is due to two components :
the DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge ΔQ moves
from V
DD
to ground. The resulting ΔQ/Δt is the current out
of V
DD
that is typically larger than the DC bias current. In
continuous mode, I
GATECHG
= f(QT+QB) where QT and QB
are the gate charges of the internal top and bottom
switches.
Both the DC bias and gate charge losses are proportional
to V
DD
and thus their effects will be more pronounced at
higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, RSW and external inductor RL. In
continuous mode the average output current flowing
through inductor L is chopped between the main switch
and the synchronous switch. Thus, the series resistance
looking into the LX pin is a function of both top and bottom
MOSFET R
DS(ON)
and the duty cycle (D) as follows :
RSW = R
DS(ON)
TOP x D + R
DS(ON)
BOT x (1"D) The R
DS(ON)
for both the top and bottom MOSFETs can be obtained
from the Typical Performance Characteristics curves. Thus,
to obtain I
2
R losses, simply add RSW to RL and multiply
the result by the square of the average output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
Thermal Considerations
In most applications, the RT8011/A does not dissipate
much heat due to its high efficiency. But, in applications
where the RT8011/A is running at high ambient
temperature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off and the SW node will become
high impedance. To avoid the RT8011/A from exceeding
the maximum junction temperature, the user will need to
do some thermal analysis. The goal of the thermal analysis
is to determine whether the power dissipated exceeds
the maximum junction temperature of the part. The
temperature rise is given by : T
R
= P
D
x θ
JA
Where PD is
the power dissipated by the regulator and θ
JA
is the thermal
resistance from the junction of the die to the ambient
temperature. The junction temperature, T
J
, is given by :
T
J
= T
A
+ T
R
Where T
A
is the ambient temperature.
As an example, consider the RT8011/A in dropout at an
input voltage of 3.3V, a load current of 2A and an ambient
temperature of 70°C. From the typical performance graph
of switch resistance, the R
DS(ON)
of the P-Channel switch
at 70°C is approximately 121mΩ. Therefore, power
dissipated by the part is :
P
D
= (I
LOAD
)
2
(R
DS(ON)
) = (2A)
2
(121mΩ) = 0.484W
For the DFN3x3 package, the θ
JA
is 110°C/W. Thus the
junction temperature of the regulator is : TJ = 70°C +
(0.484W) (110°C/W) = 123.24°C Which is below the
maximum junction temperature of 125°C. Note that at
higher supply voltages, the junction temperature is lower
due to reduced switch resistance (R
DS(ON)
).
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ΔI
LOAD(ESR)
, where ESR is the effective series
RT8011/A
14
DS8011/A-02 March 2011www.richtek.com
Figure 7. RT8011 Demo Board
Figure 8. RT8011A Demo Board (Only WDFN-8EL 3x3)
resistance of C
OUT
. ΔI
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used
by the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability problem.
The COMP pin external components and output capacitor
shown in Typical Application Circuit will provide adequate
compensation for most applications.
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of RT8011/A.
` A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the GND pin at one point that is then connected to
the PGND pin close to the IC. The exposed pad should
be connected to GND.
` Connect the terminal of the input capacitor(s), C
IN
, as
close as possible to the PVDD pin. This capacitor
provides the AC current into the internal power
MOSFETs.
` LX node is with high frequency voltage swing and should
be kept small area. Keep all sensitive small-signal nodes
away from LX node to prevent stray capacitive noise
pick-up.
` Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of powercomponents.
You can connect the copper areas to any DC net (PVDD,
VDD, VOUT, PGND, GND, or any other DC rail in your
system).
` Connect the FB pin directly to the feedback resistors.
The resistor divider must be connected between V
OUT
and GND.
RT8011/A
15
DS8011/A-02 March 2011 www.richtek.com
Outline Dimension
Dimensions In Millimeters Dimensions In Inches
Symbol
Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.180 0.300 0.007 0.012
D 2.950 3.050 0.116 0.120
D2 2.200 2.700 0.087 0.106
E 2.950 3.050 0.116 0.120
E2 1.450 1.750 0.057 0.069
e 0.500 0.020
L 0.350 0.450
0.014 0.018
W-Type 8EL DFN 3x3 Package (0.5mm Lead Pitch)
1
1
2
2
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
DETAIL A
Pin #1 ID and Tie Bar Mark Options
D
1
E
A3
A
A1
D2
E2
L
b
e
SEE DETAIL A

RT8011GQW

Mfr. #:
Manufacturer:
Description:
IC REG BUCK ADJUSTABLE 2A 10WDFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet