MAX4510EUT+T

MAX4510/MAX4520
Rail-to-Rail, Fault-Protected,
SPST Analog Switches
_______________________________________________________________________________________ 7
0
0.5
1.5
1.0
2.5
2.0
3.0
010155 20253035
LOGIC-LEVEL THRESHOLD vs. V+
MAX4511-10
V+ (V)
LOGIC-LEVEL THRESHOLD (V)
Typical Operating Characteristics (continued)
(T
A
= +25°C, unless otherwise noted.)
0
-100
0.01 1 100.1 1000
FREQUENCY RESPONSE
MAX4510/20 TOC11
FREQUENCY (MHz)
LOSS (dB)
-90
-80
-70
-60
-50
-40
-30
-20
-10
100
-110
OFF LOSS
ON LOSS
V+ = +15V
V- = -15V
Pin Description
Detailed Description
Overview of Traditional
Fault-Protected Switches
The MAX4510/MAX4520 are fault-protected CMOS
analog switches with unusual operation and construc-
tion. Traditional fault-protected switches are construct-
ed by three series FETs. This produces good off
characteristics, but fairly high on-resistance when the
signals are within about 3V of each supply rail. As the
voltage on one side of the switch approaches within
about 3V of either supply rail (a fault condition), the
switch impedance becomes higher, limiting the output
signal range (on the protected side of the switch) to
approximately 3V less than the appropriate polarity
supply voltage.
During a fault condition, the output current that flows
from the protected side of the switch into its load comes
from the fault source on the other side of the switch. If
the switch is open or the load is extremely high imped-
ance, the input current will be very low. If the switch is
on and the load is low impedance, enough current will
flow from the source to maintain the load voltage at 3V
less than the supply.
1
3
2, 7
µMAX
4
6
PIN
5
8
SOT23-6
Analog Switch Common
Terminal
COM5
Fault-Protected Analog
Switch—normally closed
(NC) for MAX4510;
normally open (NO) for
MAX4520
NC or NO6
No Connection. Not inter-
nally connected.
N.C.
GroundGND4
Logic Control Digital InputIN3
Negative Supply Voltage
Input. Connect to GND for
single-supply operation.
V-2
Positive Supply Voltage
Input
V+1
FUNCTIONNAME
MAX4510/MAX4520
Rail-to-Rail, Fault-Protected,
SPST Analog Switches
8 _______________________________________________________________________________________
Overview of MAX4510/MAX4520
The MAX4510/MAX4520 differ considerably from tradi-
tional fault-protection switches, with several advan-
tages. First, they are constructed with two parallel
FETs, allowing very low on-resistance when the switch
is on. Second, they allow signals on the NC or NO pins
that are within or slightly beyond the supply rails to be
passed through the switch to the COM terminal, allow-
ing rail-to-rail signal operation. Third, when a signal on
NC or NO exceeds the supply rails by about 50mV (a
fault condition), the voltage on COM is limited to the
appropriate polarity supply voltage. Operation is identi-
cal for both fault polarities. The fault-protection extends
to ±36V from GND.
During a fault condition, the NO or NC input pin
becomes high impedance regardless of the switch
state or load resistance. If the switch is on, the COM
output current is furnished from the V+ or V- pin by
“booster” FETs connected to each supply pin. These
FETs can typically source or sink up to 13mA.
When power is removed, the fault protection is still in
effect. In this case, the NO or NC terminals are a virtual
open circuit. The fault can be up to ±40V.
The COM pin is not fault protected; it acts as a normal
CMOS switch pin. If a voltage source is connected to
the COM pin, it should be limited to the supply volt-
ages. Exceeding the supply voltage will cause high
currents to flow through the ESD protection diodes,
possibly damaging the device (see Absolute Maximum
Ratings).
Internal Construction
Internal construction is shown in Figure 1, with the ana-
log signal paths shown in bold. A single normally open
(NO) switch is shown; the normally closed (NC) config-
uration is identical except the logic-level translator
becomes an inverter. The analog switch is formed by
the parallel combination of N-channel FET N1 and P-
channel FET P1, which are driven on and off simultane-
ously according to the input fault condition and the
logic-level state.
V+
NO
(NC)
IN
GND
V-
HIGH
FAULT
LOW
FAULT
ON
N1
P1
P2
COM
N2
NC SWITCH
-ESD DIODE
NORMALLY OPEN SWITCH CONSTRUCTION
MAX4510
MAX4520
Figure 1. Functional Diagram
MAX4510/MAX4520
Rail-to-Rail, Fault-Protected,
SPST Analog Switches
_______________________________________________________________________________________ 9
Normal Operation
Two comparators continuously compare the voltage on
the NO (or NC) pin with V+ and V-. When the signal on
NO or NC is between V+ and V-, the switch acts nor-
mally, with FETs N1 and P1 turning on and off in
response to IN signals. The parallel combination of N1
and P1 forms a low-value resistor between NO (or NC)
and COM so that signals pass equally well in either
direction.
Positive Fault Condition
When the signal on NO (or NC) exceeds V+ by about
50mV, the high-fault comparator output is high, turning
off FETs N1 and P1. This makes the NO (or NC) pin
high impedance regardless of the switch state. If the
switch state is “off,” all FETs are turned off and both NO
(or NC) and COM are high impedance. If the switch
state is “on,” FET P2 is turned on, sourcing current from
V+ to COM.
Negative Fault Condition
When the signal on NO (or NC) exceeds V- by about
50mV, the low-fault comparator output is high, turning
off FETs N1 and P1. This makes the NO (or NC) pin
high impedance regardless of the switch state. If the
switch state is “off,” all FETs are turned off and both NO
(or NC) and COM are high impedance. If the switch
state is “on,” FET N2 is turned on, sinking current from
COM to V-.
Transient Fault Response and Recovery
When a fast rise-time and fall-time transient on IN
exceeds V+ or V-, the output (COM) follows the input (IN)
to the supply rail with only a few nanoseconds delay.
This delay is due to the switch on-resistance and circuit
capacitance to ground. When the input transient returns
to within the supply rails, however, there is a longer out-
put recovery time delay. For positive faults, the recovery
time is typically 3.5µs. For negative faults, the recovery
time is typically 1.3µs. These values depend on the COM
output resistance and capacitance. The delays are not
dependent on the fault amplitude. Higher COM output
resistance and capacitance increase recovery times.
COM and IN Pins
FETs N2 and P2 can source about ±13mA from V+ or V-
to the COM pin in the fault condition. Ensure that if the
COM pin is connected to a low-resistance load, the
absolute maximum current rating of 30mA is never
exceeded, both in normal and fault conditions.
The GND, COM, and IN pins do not have fault protec-
tion. Reverse ESD-protection diodes are internally con-
nected between GND, COM, IN, and both V+ and V-. If a
signal on GND, COM, or IN exceeds V+ or V- by more
than 300mV, one of these diodes will conduct heavily.
During normal operation these reverse-biased ESD
diodes leak a few nanoamps of current to V+ and V-.
Fault-Protection Voltage and Power Off
The maximum fault voltage on the NC or NO pins is
±36V with power applied and ±40V with power off.
Failure Modes
The MAX4510/MAX4520 are not lightning arrestors or
surge protectors.
Exceeding the fault-protection voltage limits on NO or
NC, even for very short periods, can cause the device
to fail.
Ground
There is no connection between the analog signal path
and GND. The analog signal path consists of an N-
channel and P-channel MOSFET with their sources and
drains paralleled and their gates driven out of phase to
V+ and V- by the logic-level translators.
V+ and GND power the internal logic and logic-level
translators and set the input logic thresholds. The logic-
level translators convert the logic levels to switched V+
and V- signals to drive the gates of the analog switch.
This drive signal is the only connection between the
power supplies and the analog signal. GND, IN, and
COM have ESD-protection diodes to V+ and V-.
IN Logic-Level Thresholds
The logic-level thresholds are CMOS and TTL compati-
ble when V+ is +15V. As V+ is raised, the threshold
increases slightly, and when V+ reaches 25V, the level
threshold is about 2.8V—above the TTL output high-
level minimum of 2.4V, but still compatible with CMOS
outputs (see Typical Operating Characteristics).
Increasing V- has no effect on the logic-level thresholds,
but it does increase the gate-drive voltage to the signal
FETs, reducing their on-resistance.
Dual Supplies
The MAX4510/MAX4520 operate with dual supplies
between ±4.5V and ±20V. The V+ and V- supplies
need not be symmetrical, but their difference cannot
exceed the absolute maximum rating of 44V.
Single Supply
The MAX4510/MAX4520 operate from a single supply
between +9V and +36V when V- is connected to GND.

MAX4510EUT+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog Switch ICs Fault-Protected SPST Analog Switch
Lifecycle:
New from this manufacturer.
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