8
AT25128A/256A [Preliminary]
3368D–SEEPR–6/04
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
one of four levels of protection. The AT25128A/256A is divided into four array segments.
Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of
the data within any selected segment will therefore be READ only. The block write pro-
tection levels and corresponding status register control bits are shown in Table 4.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties
and functions as the regular memory cells (e.g. WREN, t
WC
, RDSR).
The WRSR instruction also allows the user to enable or disable the write protect (WP
)
pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is
enabled when the WP
pin is low and the WPEN bit is “1”. Hardware write protection is
disabled when
either
the WP pin is high or the WPEN bit is “0.” When the device is hard-
ware write protected, writes to the Status Register, including the Block Protect bits and
the WPEN bit, and the block-protected sections in the memory array are disabled.
Writes are only allowed to sections of the memory which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to
“0”, as long as the WP
pin is held low.
READ SEQUENCE (READ): Reading the AT25128A/256A via the SO (Serial Output)
pin requires the following sequence. After the CS
line is pulled low to select a device,
the READ op-code is transmitted via the SI line followed by the byte address to be read
(Refer to Table 6). Upon completion, any data on the SI line will be ignored. The data
(D7 - D0) at the specified address is then shifted out onto the SO line. If only one byte is
to be read, the CS
line should be driven high after the data comes out. The READ
sequence can be continued since the byte address is automatically incremented and
data will continue to be shifted out. When the highest address is reached, the address
counter will roll over to the lowest address allowing the entire memory to be read in one
continuous READ cycle.
Table 4. Block Write Protect Bits
Level
Status Register Bits Array Addresses Protected
BP1 BP0 AT25128A AT25256A
0 0 0 None None
1(1/4) 0 1 3000 - 3FFF 6000 - 7FFF
2(1/2) 1 0 2000 - 3FFF 4000 - 7FFF
3(All) 1 1 0000 - 3FFF 0000 - 7FFF
Table 5. WPEN Operation
WPEN WP WEN
Protected
Blocks
Unprotected
Blocks
Status
Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable
