MP6902- FAST TURN-OFF INTELLIGENT CONTROLLER
MP6902 Rev. 1.14 www.MonolithicPower.com 7
6/23/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
OPERATION
The MP6902 supports operation in DCM and
Quasi-Resonant Flyback converters. The control
circuitry controls the gate in forward mode and
will turn the gate off when the MOSFET current is
fairly low.
Blanking
The control circuitry contains a blanking function.
When it pulls the MOSFET on/off, it makes sure
that the on/off state at least lasts for some time.
The turn on blanking time is ~1.6us, which
determines the minimum on-time. During the turn
on blanking period, the turn off threshold is not
totally blanked, but changes the threshold
voltage to ~+50mV (instead of -30mV). This
assures that the part can always be turned off
even during the turn on blanking period. (Albeit
slower)
VD Clamp
Because V
D
can go as high as 180V, a High-
Voltage JFET is used at the input. To avoid
excessive currents when Vg goes below -0.7V, a
small resistor is recommended between V
D
and
the drain of the external MOSFET.
Under-Voltage Lockout (UVLO)
When the VDD is below UVLO threshold, the part
is in sleep mode and the Vg pin is pulled low by a
10kΩ resistor.
Enable pin
If EN is pulled low, the part is in sleep mode.
Thermal shutdown
If the junction temperature of the chip exceeds
170
o
C, the Vg will be pulled low and the part
stops switching. The part will return to normal
function after the junction temperature has
dropped to 120
o
C.
Thermal Design
If the dissipation of the chip is higher than
100mW due to switching frequencies above
100kHz.
Turn-on Phase
When the synchronous MOSFET is conducting,
current will flow through its body diode which
generates a negative Vds across it. Because this
body diode voltage drop (<-500mV) is much
smaller than the turn on threshold of the control
circuitry (-70mV), which will then pull the gate
driver voltage high to turn on the synchronous
MOSFET after about 150ns turn on delay
(Defined in Figure 2).
As soon as the turn on threshold (-70mV) is
triggered, a blanking time (Minimum on-time:
~1.6us) will be added during which the turn off
threshold will be changed from -30mV to +50mV.
This blanking time can help to avoid error trigger
on turn off threshold caused by the turn on
ringing of the synchronous MOSFET.
V
DS
V
GATE
t
Don
t
Doff
-70mV
-30mV
2V
Total
t
5V
Figure 2—Turn on and Turn off delay
Conducting Phase
When the synchronous MOSFET is turned on,
Vds becomes to rise according to its on
resistance, as soon as Vds rises above the turn
on threshold (-70mV), the control circuitry stops
pulling up the gate driver which leads the gate
voltage is pulled down by the internal pull-down
resistance (10k) to larger the on resistance of
synchronous MOSFET to ease the rise of Vds.
By doing that, Vds is adjusted to be around -
70mV even when the current through the MOS is
fairly small, this function can make the driver
voltage fairly low when the synchronous
MOSFET is turned off to fast the turn off speed
(this function is still active during turn on blanking
time which means the gate driver could still be
turned off even with very small duty of the
synchronous MOSFET).
MP6902- FAST TURN-OFF INTELLIGENT CONTROLLER
MP6902 Rev. 1.14 www.MonolithicPower.com 8
6/23/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
Turn-off Phase
When Vds rises to trigger the turn off threshold (-
30mV), the gate voltage is pulled to low after
about 20ns turn off delay (defined in Figure 2) by
the control circuitry. Similar with turn-on phase, a
200ns blanking time is added after the
synchronous MOSFET is turned off to avoid error
trigger.
Figure 3 shows synchronous rectification
operation at heavy load condition. Due to the
high current, the gate driver will be saturated at
first, during which the gate driver voltage is kept
at ~2V lower than V
DD
(when V
DD
>16V, gate
driver will be internal clamped at 14V). After Vds
goes to above -70mV, gate driver voltage
decreases to adjust the Vds to typical -70mV.
Figure 4 shows synchronous rectification
operation at light load condition. Due to the low
current, the gate driver voltage never saturates
but begins to decrease as soon as the
synchronous MOSFET is turned on and adjust
the Vds.
-70mV
-30mV
Vds
Isd
Vgs
t0 t1 t2
Figure 3—Synchronous Rectification
Operation at heavy load
-70mV
-30mV
Vds
Isd
Vgs
t0 t1 t2
Figure 4Synchronous Rectification
Operation at light load
V
DS
Spike
V
OUT
+V
IN
/n
V
DS
V
G
Figure 5—Drain-Source and Gate Driver
voltage on SR MOFET
Figure 5 shows the whole synchronous
rectification waveform on drain-source voltage
V
DS
and gate driver signal V
GS
. For safe operation
of the IC, it is required:
OUT IN DS _ Spike
V V / n V 180V * k
+
+<
Where 180V is the maximum voltage rating on V
D
pin of MP6902, V
IN
/V
OUT
is the input/output DC
voltage, n is the turn ratio from primary to
secondary of the power transformer, V
DS_Spike
is
the spike voltage on drain-source which is lead
by leakage inductance, while k is the de-rating
factor which is usually selected as 0.7~0.8.
Light-load Latch-off Function
The gate driver of MP6902 is latched to save the
driver loss at light-load condition to improve
efficiency. When the synchronous MOSFET’s
conducting period keeps lower than light load
timing (T
LL
)
for longer than the light-load-enter
delay (T
LL-Delay
), MP6902 enters light-load mode
and latches off the gate driver. Here the
synchronous MOSFET’s conducting period is
from turn on of the gate driver to the moment
when V
GS
drops to below 1V (V
LL_GS
). During
light-load mode, MP6902 monitors the
synchronous MOSFET’s body diode conducting
period by sensing the time duration of the V
DS
below -250mV(V
LL_DS
). If it is longer than T
LL
+T
LL-
H
(T
LL-H
, light-load-enter pulse width hysteresis),
the light-load mode is finished and gate driver of
MP6902 is unlatched to restart the synchronous
rectification.
MP6902- FAST TURN-OFF INTELLIGENT CONTROLLER
MP6902 Rev. 1.14 www.MonolithicPower.com 9
6/23/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
For MP6902, the light load enter timing (T
LL
) is
programmable by connecting a resistor (R
LL
) on
LL pin, by monitoring the LL pin current (the LL
pin voltage keeps at ~2V internally), T
LL
is set as
following:
LL LL
2.2 s
TR(k)
100k
μ
≈Ω
Ω
SR MOSFET Selection and Driver Ability
The Power Mosfet selection proved to be a trade
off between Ron and Qg. In order to achieve high
efficiency, the Mosfet with smaller Ron is always
preferred, while the Qg is usually larger with
smaller Ron, which makes the turn-on/off speed
lower and lead to larger power loss. For MP6902,
because Vds is regulated at ~-70mV during the
driving period, the Mosfet with too small Ron is
not recommend, because the gate driver may be
pulled down to a fairly low level with too small
Ron when the Mosfet current is still fairly high,
which make the advantage of the low Ron
inconspicuous.
Figure 6 shows the typical waveform of QR
flyback. Assume 50% duty cycle and the output
current is I
OUT
.
To achieve fairly high usage of the Mosfet’s Ron,
it is expected that the Mosfet be fully turned on at
least 50% of the SR conduction period:
OUT
Vds Ic Ron 2 I Ron Vfwd=− × =− × ≤−
Where V
ds
is Drain-Source voltage of the Mosfet
and V
fwd
is the forward voltage threshold of
MP6902, which is ~70mV.
So the Mosfet’s Ron is recommended to be no
lower than ~35/I
OUT
(m). (For example, for 5A
application, the Ron of the Mosfet is
recommended to be no lower than 7m)
Figure 7 shows the corresponding total delay
during turn-on period (t
Total
, see Figure 2) with
driving different Qg Mosfet by MP6902. From
Figure 7, with driving a 120nC Qg Mosfet, the
driver ability of MP6902 is able to pull up the gate
driver voltage of the Mosfet to ~5V in 300ns as
soon as the body diode of the Mosfet is
conducting, which greatly save the turn-on power
loss in the Mosfet’s body diode.
Id
Ipeak
Vg
SR Conduction Period
50% SR Conduction Period
Ic
Ipeak˜ 4·I
OUT
Ic˜ I
OUT
Figure 6—Synchronous Rectification typical
waveforms in QR Flyback
Turn-on Delay vs. Qg
0
50
100
150
200
250
300
350
0 20 40 60 80 100 120 140
Qg (nC)
Total Delay (ns )
Figure 7—Total Turn-on Delay vs. Qg
Typical System Implementations
6
1
5
8
3
4
MP6902
R1
R3
C1
C2
C3
VD VDD
PGND
LL
VSSVG
EN
R2
2
Figure 8— IC Supply derived directly from
Output Voltage
Figure 8 shows the typical system
implementation for the IC supply derived from
output voltage, which is available in low-side
rectification and the output voltage is
recommended to be in the V
DD
range of MP6902
(from 8V to 24V).
If output voltage is out of the V
DD
range of
MP6902 or high-side rectification is used, it is
recommended to use an auxiliary winding from
the power transformer for the IC supply, which is
shown in Figure 9 and Figure.10.

MP6902DS-LF

Mfr. #:
Manufacturer:
Monolithic Power Systems (MPS)
Description:
AC/DC Converters Fast-Off Intelligent Rectifier Driver
Lifecycle:
New from this manufacturer.
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