74HCT32DTR2G

74HCT32
http://onsemi.com
4
DC CHARACTERISTICS (Voltages Referenced to GND)
V
CC
(V)
Guaranteed Limit
Symbol Parameter Condition 55 to 25°C 85°C 125°C Unit
V
IH
Minimum HighLevel Input Voltage V
out
= 0.1V
|I
out
| 20mA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
V
IL
Maximum LowLevel Input Voltage V
out
= V
CC
0.1V
|I
out
| 20mA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
OH
Minimum HighLevel Output
Voltage
V
in
= V
IL
|I
out
| 20mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
V
in
= V
IL
|I
out
| 4.0mA 4.5 3.98 3.84 3.70
V
OL
Maximum LowLevel Output
Voltage
V
in
= V
IH
|I
out
| 20mA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
|I
out
| 4.0mA 4.5 0.26 0.33 0.40
I
in
Maximum Input Leakage Current V
in
= V
CC
or GND 5.5 ±0.1 ±1.0 ±1.0
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0mA
5.5 2.0 20 40
mA
DI
CC
Additional Quiescent Supply
Current
V
in
= 2.4V, Any One Input
V
in
= V
CC
or GND, Other Inputs
I
out
= 0mA
5.5
55°C 25 to 125°C
mA
2.9 2.4
1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
2. Total Supply Current = I
CC
+ ΣDI
CC
.
AC CHARACTERISTICS (C
L
= 50pF, Input t
r
= t
f
= 6ns)
V
CC
(V)
Guaranteed Limit
Symbol Parameter 55 to 25°C 85°C 125°C Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
4.5 15 19 22 ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
4.5 15 19 22 ns
C
in
Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor HighSpeed CMOS Data Book (DL129/D).
C
PD
Power Dissipation Capacitance (Per Buffer)*
Typical @ 25°C, V
CC
= 5.0 V, V
EE
= 0 V
pF
20
* Used to determine the noload dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
. For load considerations, see Chapter 2 of the
ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
74HCT32
http://onsemi.com
5
Figure 1. Switching Waveforms
OUTPUT Y
INPUT
A OR B
C
L
*
*Includes all probe and jig capacitance
TEST
POINT
90%
50%
10%
t
TLH
DEVICE
UNDER
TEST
OUTPUT
Figure 2. Test Circuit
Y
A
B
Figure 3. Expanded Logic Diagram
(1/4 of the Device)
t
THL
t
PLH
t
PHL
t
r
t
f
GND
V
CC
90%
50%
10%
74HCT32
http://onsemi.com
6
PACKAGE DIMENSIONS
SOIC14
CASE 751A03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
A
B
G
P 7 PL
14
8
7
1
M
0.25 (0.010) B
M
S
B
M
0.25 (0.010) A
S
T
T
F
R X 45
SEATING
PLANE
D 14 PL
K
C
J
M
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
__ __
7.04
14X
0.58
14X
1.52
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
7X
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

74HCT32DTR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Logic Gates QUAD OR GATE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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