SST39VF3201-70-4I-EKE-T

©2011 Silicon Storage Technology, Inc. DS25028A 08/11

SST39VF1601 / SST39VF3201

SST39VF1602 / SST39VF3202

Not Recommended for New Designs

Microchip Technology Company

for timing waveforms and Figure 24 for the flowchart. Any commands issued during the Sector- or

Block-Erase operation are ignored. When WP# is low, any attempt to Sector- (Block-) Erase the pro-

tected block will be ignored. During the command sequence, WP# should be statically held high or low.

The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing

data to be read from any memory location, or program data into any sector/block that is not suspended

for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-

To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue

Erase Resume command. The operation is executed by issuing one byte command sequence with

Erase Resume command (30H) at any address in the last Byte sequence.

The SST39VF160x/320x provide a Chip-Erase operation, which allows the user to erase the entire

memory array to the “1” state. This is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase

command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the ris-

ing edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid

read is Toggle Bit or Data# Polling. See Table 6 for the command sequence, Figure 10 for timing dia-

tus bits: Data# Polling (DQ

the rising edge of WE#, which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a

Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this

occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with

either DQ

or DQ

. In order to prevent spurious rejection, if an erroneous result occurs, the software

routine should include a loop to read the accessed location an additional two (2) times. If both reads

are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

©2011 Silicon Storage Technology, Inc. DS25028A 08/11

SST39VF1601 / SST39VF3201

SST39VF1602 / SST39VF3202

Not Recommended for New Designs

Microchip Technology Company

true data. Note that even though DQ

may have valid data immediately following the completion of an internal

Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in

subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt

to read DQ

will produce a ‘0’. Once the internal Erase operation is completed, DQ

The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For

Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#)

pulse. See Figure 7 for Data# Polling timing diagram and Figure 21 for a flowchart.

alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation

is completed, the DQ

, Block-, or Chip-Erase, the toggle bit (DQ

Write operation. See Figure 8 for Toggle Bit timing diagram and Figure 21 for a flowchart.

©2011 Silicon Storage Technology, Inc. DS25028A 08/11

SST39VF1601 / SST39VF3201

SST39VF1602 / SST39VF3202

Not Recommended for New Designs

Microchip Technology Company

tects the bottom 32 KWord block of the device. The Boot Block address ranges are described in Table

3. Program and Erase operations are prevented on the 32 KWord when WP# is low. If WP# is left float-

ing, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program

and Erase operations on that block.