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NLSF308MNR2G

P1-P3P4-P5
© Semiconductor Components Industries, LLC, 2006
May, 2006 − Rev. 4
1 Publication Order Number:
NLSF308/D
NLSF308
Quad 2−Input AND Gate
The NLSF308 is an advanced high speed CMOS 2−input AND gate
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
• High Speed: t
PD
= 4.3 ns (Typ) at V
CC
= 5.0 V
• Low Power Dissipation: I
CC
= 2.0 mA (Max) at T
A
= 25°C
• High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 5.5 V Operating Range
• Low Noise: V
OLP
= 0.8 V (Max)
• Function Compatible with Other Standard Logic Families
• QFN−16 Package
• Latchup Performance Exceeds 300 mA
• ESD Performance: Human Body Model; > 2000 V;
Machine Model; > 200 V
• Chip Complexity: 24 FETs or 6 Equivalent Gates
• Pb−Free Package is Available*
L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs Output
AB
L
L
L
H
Y
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
Device Package Shipping
†
ORDERING INFORMATION
NLSF308MNR2 QFN−16 3000 / Tape & Ree
l
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
NLSF308MNR2G QFN−16
(Pb−Free)
3000 / Tape & Ree
l
NLSF308 = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
MARKING DIAGRAM
QFN−16
MN SUFFIX
CASE 485G
16
NLSF
308
ALYW G
G
1
1
NLSF308
http://onsemi.com
2
1
Y1
15
A1
Figure 1. LOGIC DIAGRAM
16
B1
5
Y2
3
A2
4
B2
7
Y3
8
A3
9
B3
10
Y4
12
A4
13
B4
Y = AB
13141516
5678
9
10
11
12
A3
A4
NC
Y4
B3
Y3
GND
Y2
B4
V
CC
A1
B1
Y1
NC
A2
B2
NLSF308
MN Package
(Top View)
1
2
3
4
Figure 2. PIN ASSIGNMENT (QFN−16)
MAXIMUM RATINGS
Parameter Symbol Value Unit
DC Supply Voltage V
CC
–0.5 to + 7.0 V
DC Input Voltage V
in
–0.5 to + 7.0 V
DC Output Voltage V
out
–0.5 to V
CC
+ 0.5 V
Input Diode Current I
IK
−20 mA
Output Diode Current I
OK
±20 mA
DC Output Current, per Pin I
out
±25 mA
DC Supply Current, V
CC
and GND Pins I
CC
±50 mA
Power Dissipation in Still Air P
D
450 mW
Storage Temperature T
stg
–65 to + 150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Max Unit
DC Supply Voltage V
CC
2.0 5.5 V
DC Input Voltage V
in
0 5.5 V
DC Output Voltage V
out
0 V
CC
V
Operating Temperature T
A
−40 + 85 °C
Input Rise and Fall Time V
CC
= 3.3 V ±0.3 V
V
CC
= 5.0 V ±0.5 V
t
r
, t
f
0
0
100
20
ns/V
NLSF308
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS
Parameter Test Conditions
V
CC
V
T
A
= 25°C T
A
= − 40 to 85°C
Uni
t
Symbol Min Typ Max Min Max
Minimum High−Level Input
Voltage
V
IH
2.0
3.0 to 5.5
1.50
V
CC
x 0.7
1.50
V
CC
x 0.7
V
Maximum Low−Level Input
Voltage
V
IL
2.0
3.0 to 5.5
0.50
V
CC
x 0.3
0.50
V
CC
x 0.3
V
Minimum High−Level Output
Voltage
V
in
= V
IH
or V
IL
I
OH
= −50 mA
V
OH
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
V
V
in
= V
IH
or V
IL
I
OH
= −4 mA,
I
OH
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
Maximum Low−Level Output
Voltage
V
in
= V
IH
or V
IL
I
OL
= 50 mA
V
OL
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
I
OL
= 4 mA
I
OL
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
Maximum Input Leakage Current V
in
= 5.5 V or GND 0 to 5.5 ± 0.1 ± 1.0
mA
Maximum Quiescent Supply
Current
V
in
= V
CC
or GND 5.5 2.0 20.0
mA
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0 ns)
Parameter Test Conditions Symbo
l
T
A
= 25°C T
A
= − 40 to 85°C
Uni
t
Min Typ Max Min Max
Maximum Propagation Delay, A or B to Y
V
CC
= 3.3 ± 0.3 V, C
L
= 15 pF,
C
L
= 50 pF
t
PLH
,
t
PHL
6.2
8.7
8.8
12.3
1.0
1.0
10.5
14.0
ns
V
CC
= 5.0 ± 0.5 V, C
L
= 15 pF,
C
L
= 50 pF
4.3
5.8
5.9
7.9
1.0
1.0
7.0
9.0
Maximum Input Capacitance C
in
4 10 10 pF
Power Dissipation Capacitance (Note 1) C
PD
Typical @ 25°C, V
CC
= 5.0 V
pF
18
1. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/4 (per gate). C
PD
is used to determine the
no−load dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
NOISE CHARACTERISTICS (Input t
r
= t
f
= 3.0 ns, C
L
= 50 pF, V
CC
= 5.0 V)
Characteristic
Symbo
l
T
A
= 25°C
Uni
t
Typ Max
Quiet Output Maximum Dynamic V
OL
V
OLP
0.3 0.8 V
Quiet Output Minimum Dynamic V
OL
V
OLV
−0.3 −0.8 V
Minimum High Level Dynamic Input Voltage V
IHD
3.5 V
Maximum Low Level Dynamic Input Voltage V
ILD
1.5 V
P1-P3P4-P5

NLSF308MNR2G

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Manufacturer:
ON Semiconductor
Description:
Logic Gates LOG QUAD 2 INPUT AND
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