CY7C1069AV33-10ZXIT

CY7C1069AV33
Document #: 38-05255 Rev. *F Page 7 of 9
Package Diagrams
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type
Operating
Range
10 CY7C1069AV33-10ZC 51-85160 54-pin TSOP II
Commercial
CY7C1069AV33-10ZXC 54-pin TSOP II (Pb-free)
CY7C1069AV33-10BAC 51-85162 60-ball (8 mm x 20 mm x 1.2 mm) FBGA
CY7C1069AV33-10ZI 51-85160 54-pin TSOP II
Industrial
CY7C1069AV33-10ZXI 54-pin TSOP II (Pb-free)
CY7C1069AV33-10BAI 51-85162 60-ball (8 mm x 20 mm x 1.2 mm) FBGA
12 CY7C1069AV33-12ZC 51-85160 54-pin TSOP II
Commercial
CY7C1069AV33-12ZXC 54-pin TSOP II (Pb-free)
CY7C1069AV33-12BAC 51-85162 60-ball (8 mm x 20 mm x 1.2 mm) FBGA
CY7C1069AV33-12ZI 51-85160 54-pin TSOP II
Industrial
CY7C1069AV33-12ZXI 54-pin TSOP II (Pb-free)
CY7C1069AV33-12BAI 51-85162 60-ball (8 mm x 20 mm x 1.2 mm) FBGA
51-85160-**
54-pin TSOP II (51-85160)
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CY7C1069AV33
Document #: 38-05255 Rev. *F Page 8 of 9
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Package Diagrams (continued)
All product and company names mentioned in this document may be the trademarks of their respective holders
DIMENSIONS IN MM
PART #
BA60A
STANDARD PKG.
BK60A
LEAD FREE PKG.
PKG WEIGHT: 0.30 gms
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(48X)
Ø0.25MCAB
Ø0.05MC
B
A
0.15(4X)
0.21±0.05
1.20 MAX
C
SEATING PLANE
0.53±0.05
0.25 C
0.15 C
A1 CORNER
TOP VIEW
BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
65
465231
8.00±0.10
20.00±0.10
A
20.00±0.10
8.00±0.10
B
1.875
2.625
G
H
D
G
H
E
F
B
C
A
18.00
6.00
DUMMY BALL (0.3) X12
0.36
0.75
1.00
0.75
1.00
60-ball FBGA (8 mm x 20 mm x 1.2 mm) (51-85162)
51-85162-*D
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CY7C1069AV33
Document #: 38-05255 Rev. *F Page 9 of 9
Document History Page
Document Title: CY7C1069AV33 2M x 8 Static RAM
Document Number: 38-05255
REV. ECN NO.
Issue
Date
Orig. of
Change Description of Change
** 113724 03/27/02 NSL New Data Sheet
*A 117060 07/31/02 DFP Removed 15-ns bin
*B 117990 08/30/02 DFP Added 8-ns bin
Changing I
CC
for 8, 10, 12 bins
t
power
changed from 1 µs to 1 ms
Load Cap Comment changed (for Tx line load)
t
SD
changed to 5.5 ns for the 10-ns bin
Changed some 8-ns bin #'s (t
HZ
, t
DOE
, t
DBE
)
Removed hz < lz comments
*C 120385 11/13/02 DFP Final Data Sheet
Added note 4 to “AC Test Loads and Waveforms” and note 7 to t
pu
and t
pd
Updated Input/Output Caps (for 48BGA only) to 8 pf/10 pf and for the 54-pin
TSOP to 6/8 pf
*D 124441 2/25/03 MEG Changed ISB1 from 100 mA to 70 mA
Shaded the 48fBGA product offering information
*E 403984 See ECN NXR Changed the Logic Block Diagram On page # 1
Added notes under Pin Configuration
Changed the Package diagram of 51-85162 from Rev *A to Rev *D
Changed 48-Ball FBGA to 60-Ball FBGA in Pin Configuration
Updated the Ordering Information
*F 492137 See ECN NXR Removed 8 ns speed bin from product offering
Changed the description of I
IX
from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Updated the Ordering Information
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CY7C1069AV33-10ZXIT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
SRAM 2M x 8 CPG IND Fast Async SRAM
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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