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9DBL411BKLFT

P1-P3P4-P6P7-P9
IDT
®
Four Output Low Power Differential Buffer for PCI Express for Gen1, Gen2, Gen3, and QPI 1645F—08/16/13
Advance Information
9DBL411B
Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, Gen3, and QPI
4
MLF Pin Description
PIN #
(MLF)
PIN NAME PIN TYPE DESCRIPTION
1 VDDA PWR 3.3V Power for the Analog Core
2 GNDA GND Ground for the Analog Core
3OE3# IN
Output Enable for DIF3 output. Control is as follows:
0 = enabled, 1 = Low-Low
4 DIF3C_LPR OUT
Complement clock of low power differential clock pair. (no 50ohm shunt resistor to
GND needed)
5 DIF3T_LPR OUT
True clock of low power differential clock pair. (no 50ohm shunt resistor to GND
needed)
6 VDD_IO PWR Power supply for low power differential outputs, nominal 1.05V to 3.3V
7 GND GND Ground pin
8 DIF2C_LPR OUT
Complement clock of low power differential clock pair. (no 50ohm shunt resistor to
GND needed)
9 DIF2T_LPR OUT
True clock of low power differential clock pair. (no 50ohm shunt resistor to GND
needed)
10 OE2# IN
Output Enable for DIF2 output. Control is as follows:
0 = enabled, 1 = Low-Low
11 DIF1C_LPR OUT
Complement clock of low power differential clock pair. (no 50ohm shunt resistor to
GND needed)
12 DIF1T_LPR OUT
True clock of low power differential clock pair. (no 50ohm shunt resistor to GND
needed)
13 OE1# IN
Output Enable for DIF1 output. Control is as follows:
0 = enabled, 1 = Low-Low
14 GND GND Ground pin
15 VDD_IO PWR Power supply for low power differential outputs, nominal 1.05V to 3.3V
16 DIF0C_LPR OUT
Complement clock of low power differential clock pair. (no 50ohm shunt resistor to
GND needed)
17 DIF0T_LPR OUT
True clock of low power differential clock pair. (no 50ohm shunt resistor to GND
needed)
18 OE0# IN
Output Enable for DIF0 output. Control is as follows:
0 = enabled, 1 = Low-Low
19 DIF_INC IN Complement side of differential input clock
20 DIF_INT IN True side of differential input clock
IDT
®
Four Output Low Power Differential Buffer for PCI Express for Gen1, Gen2, Gen3, and QPI 1645F—08/16/13
Advance Information
9DBL411B
Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, Gen3, and QPI
5
Absolute Maximum Ratings
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes
Maximum Supply Volta
g
e VDDA Core Supply Volta
g
e 4.6 V 1,7
Maximum Supply Voltage VDD_IO
Low-Voltage Differential I/O
0.99 3.8 V 1,7
Maximum Input Voltage
V
IH
3.3V LVCMOS Inputs 4.6 V 1,7,8
Minimum Input Voltage V
IL
Any Input Vss - 0.5 V 1,7
TambCOM Commercial Ran
g
e070°C1
TambIND Industrial Range -40 85 °C 1
Storage Temperature Ts - -65 150
°
C
1,7
Input ESD protection ESD prot Human Body Model 2000 V 1,7
Ambient Operating Temp
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes
Supply Volta
g
e VDDA Supply Volta
g
e 3.000 3.600 V 1
Supply Volta
g
e VDDxxx_IO
Low-Voltage Differential I/O
Supply 0.99 3.600 V 1
Input High Voltage
V
IHSE
Single-ended inputs 2
V
DD
+
0.3 V 1
Input Low Voltage
V
ILSE
Single-ended inputs
V
SS
- 0.3
0.8 V 1
Differential Input High
Voltage
V
IHDI F
Differential inputs
(single-ended measurement) 600 1.15 V 1
Differential Input Low
Voltage
V
ILDI
F
Differential inputs
(single-ended measurement)
V
SS
- 0.3
300 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 2
Input Leakage Current
I
IN
V
IN
= V
DD ,
V
IN
=
GND
-5 5 uA 1
I
DD_3. 3V
VDDA supply current 20 mA 1
I
DD_IO_133M
VDD_IO supply @ fOP =
133MHz 20 mA 1
I
DD_SB_3.3V
VDDA supply current, Input
stopped, OE# pins all high 750 uA 1
I
DD_SBI O
VDD_IO supply, Input
stopped, OE# pins all high 150 uA 1
Input Frequency
F
i
V
DD
= 3.3 V
15 150 MHz 2
Pin Inductance
L
p
in
7nH 1
C
IN
Logic Inputs 1.5 5 pF 1
C
OUT
Output pin capacitance 6 pF 1
OE# latency
(at least one OE# is low)
T
OE#LAT
Number of clocks to enable
or disable output from
assertion/deassertion of OE# 1 3 periods 1
Clock stabilization time
(from all OE# high to first
OE# low).
T
STAB
Delay from assertion of first
OE# to first clock out
(assumes input clock running
and device in power down
state)) 150 ns 1
Tdrive_OE#
T
DROE#
Output enable after
OE# de-assertion 10 ns 1
Tfall_OE#
T
FALL
5ns 1
Trise_OE#
T
RISE
5ns 1
Power Down Current
(All OE# pins High)
Fall/rise time of OE# inputs
Input Capacitance
Operating Supply Current
IDT
®
Four Output Low Power Differential Buffer for PCI Express for Gen1, Gen2, Gen3, and QPI 1645F—08/16/13
Advance Information
9DBL411B
Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, Gen3, and QPI
6
AC Electrical Characteristics - DIF Low Power Differential Outputs
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES
Rising Edge Slew Rate t
SLR
Differential Measurement 1.5 4 V/ns 1,2
Falling Edge Slew Rate t
FLR
Differential Measurement 1.5 4 V/ns 1,2
Slew Rate Variation t
SLVAR
Single-ended Measurement 20 % 1
Maximum Output Voltage V
HIGH
Includes overshoot 1150 mV 1
Minimum Output Voltage V
LOW
Includes undershoot -300 mV 1
Differential Voltage Swing V
SWING
Differential Measurement 1200 mV 1
Crossing Point Voltage V
XABS
Single-ended Measurement 300 550 mV 1,3,4
Crossing Point Variation V
XABSVAR
Single-ended Measurement 140 mV 1,3,5
Duty Cycle Distortion D
CYCDIS0
Differential Measurement,
fIN<=133.33MHz
3%1,6
Additive Cycle to Cycle
Jitter
DIFJ
C2CADD
Differential Measurement,
Additive
15 ps 1
DIF[3:0] Skew DIF
SKEW
Differential Measurement 50 ps 1
Propagation Delay t
PD
Input to output Delay 2.5 3.5 ns 1
Additive Phase Jitter -
PCIe Gen1
t
phase_add
PCIG1
1.5MHz < 22MHz 6
ps Pk-
Pk
1,9
Additive Phase Jitter -
PCIe Gen2 High Band
t
phase_add
PCIG2HI
High Band is 1.5MHz to
Nyquist (50MHz)
0.16 ps rms 1,9
Additive Phase Jitter PCIe
Gen2 Low Band
t
phase_add
PCIG2LO
Low Band is 10KHz to
1.5MHz
0.07 ps rms 1,9
Additive Phase Jitter PCIe
Gen3
t
phase_add
PCIG2LO
2M-4M, 2M-5M filter 0.2 ps rms 1,9
Additive Phase Jitter
QPI133 (6.4GBs, 12 UI)
t
phase_add
QPI6G4
11MHz to 33MHz 0.04 ps rms 1,9
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through Vswing centered around differential zero
3
Vxabs is defined as the voltage where CLK = CLK#
4
Only applies to the differential rising edge (CLK rising and CLK# falling)
9
The 9DBL411B has no PLL, so the part itself contributes very little jitter to the input clock. But this also means that the 9DBL411
cannot 'de-jitter' a noisy input clock. Values calculated per PCI SIG and per Intel Clock Jitter tool version 1.5
8
Maximum input voltage is not to exceed maximum VDD
6
This figure refers to the maximum distortion of the input wave form.
5
Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and
falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.
7
Operation under these conditions is neither implied, nor guaranteed.
Notes on Electrical Characteristics (all measurements use 9LRS3187B as clock source and R
S
=33ohms/C
L
=2pF
test load
)
:
P1-P3P4-P6P7-P9

9DBL411BKLFT

Mfr. #:
Buy 9DBL411BKLFT
Manufacturer:
IDT
Description:
Clock Buffer LOW POWER PCIE/QPI w /POWER DOWN FEATURE
Lifecycle:
New from this manufacturer.
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