STAC9753XXTAEB2XR Datasheet STAC9753XXTAEB2X, STAC9753XXTAEB2XR | P46-P48

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

46 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

7.4. PC Beep Implementation

The STAC9752/9753 offers 2 styles of PC BEEP, Analog and Digital. The digital PC Beep is a new

feature added to the AC’97 Specification Rev 2.3. This style of PC Beep will eventually replace the

analog style, thus eliminating the need for a PC Beep pin. Until this feature is widely accepted, IDT

will provide BOTH styles of PC Beep. Both PC Beep styles use Reg 0Ah. Additional information

about Reg 0Ah can be found in Section8.1.5: page51.

7.4.1. Analog PC Beep

PC Beep is active on power up and defaults to an un-muted state. The PC_BEEP input is routed

directly to the MONO_OUT, LINE_OUT and HP_OUT pins of the CODEC. Because the PC_BEEP

input drive is often a full scale digital signal, some resistive attenuation of the PC_BEEP input is rec-

ommended to keep the beep tone within reasonable volume levels. The user should mute this input

before using any other mixer input because the PC Beep input can contribute noise to the lineout

during normal operation. This style of PC Beep is related to the AC’97 Specification Rev 2.2. To use

the analog PC Beep, a value of 00h written to bits F[7:0] (D[12:5]) disables the Digital PC Beep gen-

eration. PV[3:0] (D[4:1]) controls the volume level from 0 to 45dB of attenuation in 3dB steps.

7.4.2. Digital PC Beep

The Digital PC Beep uses the identical register as the analog style, Reg 0Ah. This register controls

the level and frequency for the PC Beep. The beep frequency is the result of dividing the 48 KHz

clock by 4 times the number specified in F[7:0], allowing tones from 47 Hz to 12 KHz. A value of 00h

written to bits F[7:0] disables the digital PC Beep generation and enables the analog PC Beep. The

volume control bits, PV[3:0] operate identically to the analog PC Beep mode. Applying a signal to the

PC Beep pin, pin 12, may cause the digital PC Beep signal to become distorted or inaudible. When

using the digital PC Beep feature, we recommend leaving the PC Beep input pin unconnected or

connected to analog ground through a capacitor. Connecting a capacitor from the PC Beep input pin

to ground will create a more pleasing sound by changing the digital output to a more sinusoidal like

output.

This will be programmed directly by the BIOS.

Table 16. Digital PC Beep Examples

Value Reg 0Ah, bits[7:0] Frequency

1 0x01 12,000 Hz

10 0x0A 1200 Hz

25 0x19 480 Hz

50 0x32 240 Hz

100 0x64 120 Hz

127 0x7F 94.48 Hz

255 0xFF 47.05 Hz

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

47 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

8. PROGRAMMING REGISTERS

Table 17. Programming Registers

Address Name Default Location

00h Reset 6A90h 8.1.1; page48

02h Master Volume 8000h 8.1.2; page48

04h HP_OUT Mixer Volume 8000h 8.1.3; page49

06h Master Volume MONO 8000h 8.1.4; page50

0Ah PC Beep Mixer Volume 0000h 8.1.5; page51

0Ch Phone Mixer Volume 8008h 8.1.6; page51

0Eh Microphone Mixer Volume 8008h 8.1.7; page52

10h Line In Mixer Volume 8808h 8.1.8; page52

12h CD Mixer Volume 8808h 8.1.9; page53

14h Video Mixer Volume 8808h 8.1.10; page53

16h Aux Mixer Volume 8808h 8.1.11; page54

18h PCM Out Mixer Volume 8808h 8.1.12; page54

1Ah Record Select 0000h 8.1.13; page55

1Ch Record Gain 8000h 8.1.14; page55

20h General Purpose 0000h 8.1.15; page56

22h 3D Control 0000h 8.1.16; page56

24h Audio Int. & Paging 0000h 8.1.17: page57

26h Powerdown Ctrl/Stat 000Fh 8.1.18; page58

28h Extended Audio ID 0A05h 8.1.19; page59

2Ah Extended Audio Control/Status 0400h* 8.1.20; page61

2Ch PCM DAC Rate BB80h 8.1.22; page63

32h PCM LR ADC Rate BB80h 8.1.23; page63

3Ah SPDIF Control 2000h 8.1.24; page64

3Eh Extended Modem Stat/Ctl 0100h 8.2.4; page65

4Ch GPIO Pin Configuration 0003h 8.2.5; page66

4Eh GPIO Pin Polarity/Type FFFFh 8.2.6; page66

50h GPIO Pin Sticky 0000h 8.2.7; page66

52h GPIO Wake-up 0000h 8.2.8; page67

54h GPIO Pin Status 0000h 8.2.9; page67

60h CODEC Class/Rev 1201h 8.3; page68

62h (Page 01h) PCI SVID FFFFh 8.4.2; page70

64h (Page 01h) PCI SSID FFFFh 8.4.3; page70

66h (Page 01h) Function Select 0000h 8.4.4; page71

68h (Page 01h) Function Information xxxxh 8.4.5; page72

6Ah Digital Audio Control 0000h 8.4.6; page73

6Ah (Page01h) Sense Details NA 8.4.7: page74

6Ch Revision Code xxxxh 8.4.7; page74

6Ch (Page01h) Reserved 0000h NA

6Eh Analog Special 1000h 8.4.9: page76

6Eh (Page01h) Reserved 0000h NA

70h Enable Register 0000h NA

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

48 STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

8.1. Register Descriptions

8.1.1. Reset (00h)

Default: 6A90h

Writing any value to this register performs a register reset, which causes all registers to revert to

their default values. This register reset also resets all the digital block. Reading this register returns

the ID code of the part.

8.1.2. Master Volume Registers (02h)

Default: 8000h

72h Analog Current Adjust 0000h 8.4.10; page77

74h EAPD Access 0800h 8.4.11; page77

78h High Pass Filter Bypass 0000h 8.4.12; page78

7Ah Reserved NA NA

7Ch Vendor ID1 8384h 8.5.1; page79

7Eh Vendor ID2 7652h 8.5.2; page79

Note: * depends upon CODEC ID

D15 D14 D13 D12 D11 D10 D9 D8

RSRVD SE4 SE3 SE2 SE1 SE0 ID9 ID8

D7 D6 D5 D4 D3 D2 D1 D0

ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

Bit(s) Reset Value Name Description

15 0 RESERVED Bit not used, should read back 0

14:10 11010 SE4:SE0 IDT ID for SS3D

9 1 ID9 20-bit ADC resolution (supported)

8 0 ID8 18-bit ADC resolution

7 1 ID7 20-bit DAC resolution (supported)

6 0 ID6 18-bit DAC resolution

5 0 ID5 Loudness (bass boost)

4 1 ID4 Headphone Out (supported)

3 0 ID3 Simulated Stereo (mono to stereo)

2 0 ID2 Bass & Treble Control

1 0 ID1 Reserved

0 0 ID0 Dedicated MIC PCM IN channel

D15 D14 D13 D12 D11 D10 D9 D8

Mute RSRVD ML5 ML4 ML3 ML2 ML1 ML0

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED MR5 MR4 MR3 MR2 MR1 MR0

Table 17. Programming Registers (Continued)

Address Name Default Location

STAC9753XXTAEB2XR

Mfr. #:

Buy STAC9753XXTAEB2XR

Manufacturer:

Tempo Semiconductor

Description:

Interface - CODECs AC97 2.3 2-CH AUDIO CODEC

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STAC9753XXTAEB2XR

STAC9753XXTAEB2XR

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