October 1997
FDV302P
Digital FET, P-Channel
General Description Features
Absolute Maximum Ratings T
A
= 25
o
C unless otherwise noted
Symbol Parameter FDV302P Units
V
DSS
Drain-Source Voltage -25 V
V
GSS
Gate-Source Voltage -8 V
I
D
Drain Current - Continuous -0.12 A
- Pulsed -0.5
P
D
Maximum Power Dissipation 0.35 W
T
J
,T
STG
Operating and Storage Temperature Range -55 to 150 °C
ESD Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
6.0 kV
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient 357 °C/W
FDV302P REV. F
-25 V, -0.12 A continuous, -0.5 A Peak.
R
DS(ON)
= 13 Ω @ V
GS
= -2.7 V
R
DS(ON)
= 10 Ω @ V
GS
= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.5V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Compact industry standard SOT-23 surface mount
package.
Replace many PNP digital transistors (DTCx and DCDx)
with one DMOS FET.
This P-Channel logic level enhancement mode field effect
transistor is produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. This
device has been designed especially for low voltage
applications as a replacement for digital transistors. Since
bias resistors are not required, this one P-channel FET can
replace several digital transistors with different bias resistors
such as the DTCx and DCDx series.
Mark:302
S
D
G
SOT-23
SuperSOT
TM
-8
SOIC-16
SO-8
SOT-223
SuperSOT
TM
-6
© 1997 Fairchild Semiconductor Corporation