© Semiconductor Components Industries, LLC, 2008
April, 2008 - Rev. 4
1 Publication Order Number:
NB6L72/D
NB6L72
2.5V / 3.3V Differential 2 X 2
Crosspoint Switch with
LVPECL Outputs
Multi-Level Inputs w/ Internal Termination
Description
The NB6L72 is a clock or data high-bandwidth fully differential 2 x
2 Crosspoint Switch with internal source termination and LVPECL
output structure, optimized for low skew and minimal jitter. The
differential inputs incorporate internal 50 W termination resistors and
will accept LVPECL, CML, LVDS, LVCMOS, or LVTTL logic levels.
The SELECT inputs are single-ended and can be driven with
LVCMOS/LVTTL.
The differential LVPECL outputs provide 800 mV output swings
when externally terminated with a 50 W resistor to V
CC
– 2.0 V.
The device is offered in a small 3 mm x 3 mm 16-pin QFN package.
The NB6L72 is a member of the ECLinPS MAXt family of high
performance clock and data management products.
Features
Input Clock Frequency > 3.0GHz
Input Data Rate > 3 Gb/s
425 ps Typical Propagation Delay
100 ps Typical Rise and Fall Times
0.5 ps maximum RMS Clock Jitter
LVPECL, CML or LVDS Input Compatible
Differential LVPECL Outputs, 800 mV Amplitude, Typical
Operating Range: V
CC
= 2.375 V to 3.63 V with GND = 0 V
Internal 50 W Input Termination Provided
Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP,
and SG Devices
-40°C to +85°C Ambient Operating Temperature
These are Pb-Free Devices
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
QFN-16
MN SUFFIX
CASE 485G
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
1
NB6L
72
ALYWG
G
16
1
NB6L72
http://onsemi.com
2
Q0
Q0
Figure 1. Logic/Block Diagram
VTD0
D0
SEL0
SEL1
Q1
22
22
2
2
2
2
2
2
V
CC
GND
+
50 W
50 W
75 kW
Q1
D0
50 W
VTD1
D1
D1
50 W
+
+
75 kW
NB6L72
http://onsemi.com
3
VTD1 D1 D1 SEL1
GND Q0 Q0 V
CC
V
CC
Q1
Q1
GND
SEL0
D0
D0
VTD0
5678
16 15 14 13
12
11
10
9
1
2
3
4
NB6L72
Exposed Pad (EP)
Figure 2. Pin Configuration (Top View)
Table 1. INPUT/OUTPUT SELECT TRUTH TABLE
SEL0* SEL1* Q0 Q1
L L D0 D0
H L D1 D0
L H D0 D1
H H D1 D1
*Defaults HIGH when left open
Table 2. PIN DESCRIPTION
Pin Name I/O Description
1 SEL0 LVTTL, LVCMOS
Input
Select Logic Input control that selects D0 or D1 to output Q0. See Table 1, Select Input
Function Table. Pin defaults HIGH when left open
2 D0 LVPECL, CML,
LVDS, LVTTL,
LVCMOS, Input
Noninverted Differential Input. Note 1.
3 D0 LVPECL, CML,
LVDS, LVTTL,
LVCMOS, Input
Inverted Differential Input. Note 1.
4 VTD0 -
Internal 50 W Termination Pin. Note 1.
5 VTD1 -
Internal 50 W termination pin. Note 1.
6 D1 LVPECL, CML,
LVDS, LVTTL,
LVCMOS, Input
Noninverted Differential Input. Note 1.
7 D1 LVPECL, CML,
LVDS, LVTTL,
LVCMOS, Input
Inverted Differential Input. Note 1.
8 SEL1 LVTTL,LVCMOS
Input
Select Logic Input control that selects D0 or D1 to output Q1. See Table 1, Select Input
Function Table. Pin defaults HIGH when left open
9 GND - Negative Supply Voltage
10 Q1 LVPECL Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
CC
- 2.0 V.
11 Q1 LVPECL Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to V
CC
- 2.0 V.
12 V
CC
- Positive Supply Voltage
13 V
CC
- Positive Supply Voltage
14 Q0 LVPECL Output
Inverted Differential Reset Input. Typically Terminated with 50 W Resistor to V
CC
- 2.0 V.
15 Q0 LVPECL Output
Noninverted Differential Reset Input. Typically Terminated with 50 W Resistor to V
CC
- 2.0 V.
16 GND - Negative Supply Voltage
- EP - The Exposed Pad (EP) on the QFN-16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat-sinking
conduit. The pad is not electrically connected to the die, but is recommended to be
electrically and thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pin (VTDn, VTDn) are connected to a common termination voltage or left open,
and if no signal is applied on Dn/Dn input, then the device will be susceptible to self-oscillation.
2. All V
CC
and GND pins must be externally connected to a power supply for proper operation.

NB6L72MNR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Analog & Digital Crosspoint ICs 2X2 PECL CROSSPOINT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet