NOVEMBER 11, 2016 19 PROGRAMMABLE CLOCK GENERATOR
5P49V5944 DATASHEET
Typical Phase Noise at 100MHz (3.3V, 25°C)
NOTE: All outputs operational at 100MHz, Phase Noise Plot with Spurs On.
PROGRAMMABLE CLOCK GENERATOR 20 NOVEMBER 11, 2016
5P49V5944 DATASHEET
5P49V5944 Application Schematic
The following figure shows an example of 5P49V5944 application schematic. Input and output terminations shown are intended as examples
only and may not represent the exact user configuration. In this example, the device is operated at V
DDD,
V
DDA
= 3.3V. The decoupling
capacitors should be located as close as possible to the power pin. A 12pF parallel resonant 8MHz to 40MHz crystal is used in this example.
Different crystal frequencies may be used. The C1 = C2 = 5pF are recommended for frequency accuracy. If different crystal types are used,
please consult IDT for recommendations. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy.
As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power
supply isolation is required. 5P49V5944 provides separate power supplies to isolate any high switching noise from coupling into the internal
PLL.
In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB
as close to the power pins as possible. If space is limited, the 0.1uf capacitor in each power pin filter should be placed on the device side. The
other components can be on the opposite side of the PCB.
Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter
performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10 kHz. If a
specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be
adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests
adding bulk capacitance in the local area of all devices.
The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables
in the datasheet to ensure the logic control inputs are properly set.
NOVEMBER 11, 2016 21 PROGRAMMABLE CLOCK GENERATOR
5P49V5944 DATASHEET
5P49V5944 Reference Schematic
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Revision history
0.1 03/05/2015 first publication
Manufacture Part Number Z@100MHz PkgSz DC res. Current(Ma)
Fair-Rite 2504021217Y0 120 0402 0.5 200
muRata BLM15AG221SN1 220 0402 0.35 300
muRata BLM15BB121SN1 120 0402 0.35 300
TDK MMZ1005S241A 240 0402 0.18 200
TECSTAR TB4532153121 120 0402 0.3 300
NOTE:FERRITE BEAD FB1 =
PLACE NEAR
I2C CONTROLLER
IF USED
LVDS TERMINATION
3.3V LVPECL TERMINATION
HCSL TERMINATION
CONFIGURATION
PULL-UP FOR
HARDWARE
CONTROL
REMOVE FOR I2C
LVCMOS TERMINATION
FOR LVDS, LVPECL AC COUPLE
USE TERMINATION ON RIGHT
5,6,7 and 20
pull-down resistors:
have weak internal
The following pins
SEE DATASHEET FOR BIAS NETWORK
Layout notes:
1. Separate Xout and Xin Traces by 3 x the trace width
2. Do not share crystal load capacitor ground via with
other components.
3. Route power from bead through bulk capacitor pad
then through 0.1uF capacitor pad then to clock chip
Vdd pad.
4. Do not share ground vias. One ground pin one ground
via.
V1P8VCA
OUT_0_SEL-I2C
FG_X1
V1P8VC
OUTR0
V1P8VC
OUTR1
SDA OUTRB1
SCL
V1P8VC
OUTR2
SD/OE OUTRB2
SDA
SCL CLKIN
OUT_0_SEL-I2C
CLKINB
V1P8VCA OUTR2
OUT_2
V1P8VC
FG_X2
V1P8VCA
VCC1P8
V3P3
V1P8VC
Size
Document Number Re v
Date: Sheet
of
0.1
Integrated Device Technology
A
11Thursday, March 05, 2015
5P49V5944A_SCH
San Jose, CA
Size
Document Number Re v
Date: Sheet
of
0.1
Integrated Device Technology
A
11Thursday, March 05, 2015
5P49V5944A_SCH
San Jose, CA
Size
Document Number Re v
Date: Sheet
of
0.1
Integrated Device Technology
A
11Thursday, March 05, 2015
5P49V5944A_SCH
San Jose, CA
C6
NP
12
R3 100
1 2
C11
.1uF
12
U2
RECEIVER
1
2
R12 50
1 2
GNDGND
Y1
25.000 MHz
CL = 8pF
4
1
2
3
R9
10K
1 2
C5
.1uF
12
C4
.1uF
12
C8
.1uF
12
R5
49.9
1%
1 2
R2
2.2
1 2
U4
RECEIVER
1
2
R14 33
1 2
U5
5P49V5944A
VDDA
3
VDD
4
XOUT
1
XIN/REF
2
SEL1/SDA
6
SEL0/SCL
7
SD/OE
5
VDDD
17
VDDO0
19
OUT0_SEL_I2CB
20
VDDO1
15
OUT1
14
OUT1B
13
VDDO2
8
OUT2
9
OUT2B
10
GND
12
GND
11
EPAD
21
EPAD
22
EPAD
23
EPAD
24
EPAD
25
GND
16
GND
18
C13 .1uF
1 2
R11 50
1 2
R10 50
1 2
C3
.1uF
12
R8
10K
1 2
R6 33
1 2
R4
49.9
1%
1 2
R15 33
1 2
C1
10uF
12
C2
1uF
12
R13 33
1 2
U3
RECEIVER
1
2
C12 .1uF
1 2
FB1
SIGNAL_BEAD
1 2
R7
10K
1 2
C7 NP
12
25.000MHz
CL=8pF

5P49V5944B000NDGI

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 1 PLL w/ Ref Clock 2 Config O/P Pairs
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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