MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
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The CLK pin now becomes an output, and provides a
single-ended replica of the differential clock signal,
which may be used to synchronize the input data. Data is
written to the device on the rising edge of the CLK signal.
Internal Reference and Control Amplifier
The MAX5854 provides an integrated 50ppm/°C, 1.24V,
low-noise bandgap reference that can be disabled and
overridden with an external reference voltage. REFO
serves either as an external reference input or an inte-
grated reference output. If REN =0, the internal refer-
ence is selected and REFO provides a 1.24V (50µA)
output. Buffer REFO with an external amplifier, when
driving a heavy load.
The MAX5854 also employs a control amplifier
designed to simultaneously regulate the full-scale out-
put current (I
FS
) for both outputs of the devices.
Calculate the output current as:
I
FS
= 32 ✕ I
REF
where I
REF
is the reference output current (I
REF
=
V
REFO
/ R
SET
) and I
FS
is the full-scale output current.
R
SET
is the reference resistor that determines the
amplifier output current of the MAX5854 (Figure 3). This
current is mirrored into the current-source array where
I
FS
is equally distributed between matched current seg-
ments and summed to valid output current readings for
the DACs.
External Reference
To disable the internal reference of the MAX5854, set
REN = 1. Apply a temperature-stable, external reference
to drive the REFO pin and set the full-scale output
(Figure 4). For improved accuracy and drift perfor-
mance, choose a fixed output voltage reference such as
the 1.2V, 25ppm/°C MAX6520 bandgap reference.
Detailed Timing
The MAX5854 accepts an input data and the DAC con-
version rate of up to 165Msps. The input latches on the
rising edge of the clock, whereas the output latches on
the following rising edge.
Figure 5 depicts the write cycle of the two DACs in non-
interleaved mode.
The MAX5854 can also operate in an interleaved data
mode. Programming the IDE bit with a high level activates
this mode (Tables 1 and 2). In interleaved mode, data for
both DAC channels is written through input port A.
Channel B data is written on the falling edge of the clock
signal and then channel A data is written on the following
rising edge of the clock signal. Both DAC outputs (chan-
nel A and B) are updated simultaneously on the next fol-
lowing rising edge of the clock. In interleaved data mode,
the maximum input data rate per channel is half of the
rate in noninterleaved mode. The interleaved data mode
is attractive for applications where lower data rates are
acceptable and interfacing on a single 10-bit bus is
desired (Figure 6).
