www.irf.com 1
12/22/05
IRF6607
Notes through are on page 10
l Application Specific MOSFETs
l Ideal for CPU Core DC-DC Converters
l Low Conduction Losses
l High Cdv/dt Immunity
l Low Profile (<0.7 mm)
l Dual Sided Cooling Compatible
l Compatible with existing Surface
Mount Techniques
Description
The IRF6607 combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFET
TM
packaging
to achieve the lowest on-state resistance in a package that has the footprint of an SO-8 and only 0.7 mm profile. The
DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly equipment and
vapor phase, infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the manu-
facturing methods and process. The DirectFET package allows dual sided cooling to maximize thermal transfer in power
systems, IMPROVING previous best thermal resistance by 80%.
The IRF6607 balances both low resistance and low charge along with ultra low package inductance to reduce both conduc-
tion and switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power
the latest generation of processors operating at higher frequencies. The IRF6607 has been optimized for parameters that
are critical in synchronous buck converters including Rds(on), gate charge and Cdv/dt-induced turn on immunity. The
IRF6607 offers particularly low Rds(on) and high Cdv/dt immunity for synchronous FET applications.
HEXFET
®
Power MOSFET
DirectFET ISOMETRIC
MT
V
DSS
R
DS
on
max
Qg(typ.)
30V
3.3m
Ω
@V
= 10V
50nC
4.4m
Ω
@V
= 4.5V
SQ SX ST MQ MX MT
Applicable DirectFET Outline and Substrate Outline (see p.9,10 for details)
Absolute Maximum Ratin
s
Parameter Units
V
DS
Drain-to-Source Voltage V
V
GS
Gate-to-Source Voltage
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
I
D
@ T
A
= 25°C
Continuous Drain Current, V
GS
@ 10V
A
I
D
@ T
A
= 70°C
Continuous Drain Current, V
GS
@ 10V
I
DM
Pulsed Drain Current
P
D
@T
A
= 25°C
Power Dissipation
P
D
@T
A
= 70°C
Power Dissipation
W
P
D
@T
C
= 25°C
Power Dissipation
Linear Derating Factor W/°C
T
J
Operating Junction and °C
T
STG
Storage Temperature Range
Thermal Resistance
Parameter Typ. Max. Units
R
θ
JA
Junction-to-Ambient ––– 35
R
θ
JA
Junction-to-Ambient 12.5 –––
R
θ
JA
Junction-to-Ambient 20 ––– °C/W
R
θ
JC
Junction-to-Case ––– 3.0
R
θ
J-PCB
Junction-to-PCB Mounted ––– 1.0
Max.
27
22
220
±12
30
94
-40 to + 150
3.6
0.029
2.3
42
PD - 94574C
