UG-203 Evaluation Board User Guide
Rev. 0 | Page 6 of 8
LOOP FILTER
The internal portion of the loop filter has two configurations:
one is for low loop bandwidth applications (~170 Hz) and the
other is for medium (~20 kHz)/high (~75 kHz) bandwidth
applications. The low loop bandwidth condition applies when
the feedback divider value (N) is 2
14
(16,384) or greater. Other-
wise, the medium/high loop bandwidth configuration is in
effect. The feedback divider value depends on the configuration
of the A[3:0] and Y[5:0] pins per Table 4.
TO
VCO
3kΩ
FILTER
53pF
C1
R
AD9550
C2
375Ω
400kΩ
BUFFER
170pF
CONTROL
LOGIC
SWITCHES CHANGE
STATE FOR N ≥ 16384
LDO
17
16
FROM
CHARGE
PUMP
09452-029
Figure 2. External Loop Filter
The bandwidth of the loop filter primarily depends on three
external components: R, C1, and C2 (labeled on the evaluation
board as R48, C15, and C3, respectively). There are two sets of
recommended values for these components corresponding to
the low and medium/high loop bandwidth configurations (see
Table 5).
Table 5. External Loop Filter Components
A[3:0] Pins R C1 C2
Loop
Bandwidth
0001 to 1100 and 1111 6.8 kΩ 47 nF 1 µF 0.17 kHz
1110
1
12 kΩ 51 pF 220 nF 20 kHz
1101 to 1110 12 kΩ 51 pF 220 nF 75 kHz
1
The 20 kHz loop bandwidth case only applies when the A[3:0] pins = 1110
and the Y[5:0] pins = 111111.
To achieve the best jitter performance in applications requiring
a loop bandwidth of less than 1 kHz, C1 and C2 must have an
insulation resistance of at least 500 ΩF.
The evaluation board comes preconfigured with the external
loop filter components required for the low loop bandwidth
setting. However, it is good practice for any frequency select pin
combination to reference Table 5 for loop filter validation. For
more detail on the AD9550 loop filter, reference the AD9550
data sheet.
PLL LOCKED INDICATOR
The PLL provides a status indicator (LOCKED) that appears at
SMA Connector J2 and LED CR2. When the PLL acquires
phase lock, the LOCKED pin switches to a Logic 1 state. When
the PLL loses lock, however, the LOCKED pin returns to a
Logic 0 state.
USING DIP SWITCHES
1. Determine the desired reference input frequency, output
frequencies, and output drivers by referencing Table 2,
Table 3, and Table 1 respectively and set the DIP switches
appropriately.
2. Reference Table 5 to confirm the preprogrammed loop
bandwidth and that the components of the evaluation
board external loop filter match those required to the
current frequency select pin combination.
3. Set up the power and signal connections to the evaluation
board according to the Evaluation Board Hardware
section.
4. Toggle the RESETB DIP switch, to apply the pin settings
and calibrate the VCO.
5. Confirm that the PLL is locked by observing the lock
detect signal via LED CR2 or SMA Connector J2. If this
signal is low, confirm the reference input frequency and
external loop filter components. If these are correct, initiate
another VCO calibration by toggling the RESETB DIP
switch again.
6. Observe the output via the connected lab measurement
equipment.
