OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

FST16232MTDX

P1-P3P4-P6
www.fairchildsemi.com 4
FST16232
AC Electrical Characteristics
Note 6: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance (Note 7)
Note 7: T
A
= +25°C, f = 1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50 Ω source terminated in 50 Ω
Note: C
L
includes load and stray capacitance
Note: Input PRR = 1.0 MHz, t
W
= 500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
Symbol Parameter
T
A
= −40 °C to +85 °C,
Units Conditions
Figure
No.
C
L
= 50pF, RU = RD = 500Ω
V
CC
= 4.5 – 5.5V V
CC
= 4.0V
Min Max Min Max
f
MAX
Maximum Clock Frequency 150 150 MHz V
I
= OPEN Figure 1
Figure 2
t
PHL
, t
PLH
Prop Delay Bus to Bus (Note 6) 0.25 0.25 ns V
I
= OPEN Figure 1
Figure 2
t
PHL
, t
PLH
Prop Delay CLK to B or A 2.0 6.3 6.0 ns V
I
= OPEN Figure 1
Figure 2
t
PZH
, t
PZL
Output Enable Time
1.7 8.5 9.0 ns
V
I
= 7V for t
PZL
, Figure 1
Figure 2
CLK to A = B
1
= B
2
V
I
= OPEN for t
PZH
Output Enable Time
2.0 6.5 6.5 ns
V
I
= 7V for t
PZL
, Figure 1
Figure 2
CLK to A or B
1
or B
2
V
I
= OPEN for t
PZH
t
PHZ
, t
PLZ
Output Disable Time
1.0 8.5 9.0 ns
V
I
= 7V for t
PLZ
, Figure 1
Figure 2
CLK to A or B V
I
= OPEN for t
PHZ
t
S
Setup Time S
1
, S
0
before CLK ↑ 2.5 2.8
ns
Figure 1
Figure 2
Setup Time CLKEN before CLK ↑ 1.8 2.0
t
H
Hold Time S
1
, S
0
after CLK ↑ 1.0 1.0
ns
Figure 1
Figure 2
Hold Time CLKEN after CLK ↑ 1.5 1.5
t
W
Pulse Width 3.1 3.1 ns Clock HIGH or LOW Figure 1
Figure 2
Symbol Parameter Typ Max Units Conditions
C
IN
Control pin Input Capacitance 4 pF V
CC
= 5.0V
C
I/O
Input/Output Capacitance 7 pF V
CC
= 5.0V, S
0
, S
1
= 0V
5 www.fairchildsemi.com
FST16232
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS56A
www.fairchildsemi.com 6
FST16232 Synchronous 16-Bit to 32-Bit Multiplexer/Demultiplexer Bus Switch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
P1-P3P4-P6

FST16232MTDX

Mfr. #:
Buy FST16232MTDX
Manufacturer:
ON Semiconductor
Description:
MUX/DEMUX 16-32BIT SYNC 56TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet