HMC8038LP4CETR

Data Sheet HMC8038
Rev. A | Page 9 of 11
THEORY OF OPERATION
The HMC8038 requires a single-supply voltage applied to the
V
DD
pin. Bypassing capacitors are recommended on the supply
line to minimize RF coupling.
The HMC8038 is controlled via two digital control voltages
applied to the V
CTL
pin and the EN pin. A small bypassing
capacitor is recommended on these digital signal lines to
improve the RF signal isolation.
The HMC8038 is internally matched to 50 Ω at the RF input
port (RFC) and the RF output ports (RF1 and RF2); therefore,
no external matching components are required. The RFx pins
are dc-coupled, and dc blocking capacitors are required on the
RF lines. The design is bidirectional; the input and outputs are
interchangeable.
The ideal power-up sequence is as follows:
1. Power up GND.
2. Power up V
DD
.
3. Power up the digital control inputs. The relative order of
the logic control inputs are not important. Powering the digital
control inputs before the V
DD
supply can inadvertently
forward bias and damage ESD protection structures.
4. Power up the RF input.
With the EN pin is logic low, the HMC8038 has two operation
modes: on and off. Depending on the logic level applied to the
V
CTL
pin, one RF output port (for example, RF1) is set to on
mode, by which an insertion loss path is provided from the
input to the output, as the other RF output port (for example,
RF2) is set to off mode, by which the output is isolated from the
input. When the RF output port (RF1 or RF2) is in isolation
mode, internally terminate it to 50 Ω, and the port absorbs the
applied RF signal.
When the EN pin is logic high, the EN pin sets the HMC8038
switch to off mode. In off mode, both output ports are isolated
from the input, and the RFC port is open reflective.
Table 7. Switch Operation Mode
Digital Control Inputs Switch Mode
V
EN
V
CTL
RFC to RF1 RFC to RF2
0 0
Off mode. The RF1 port is isolated from the RFC port and
is internally terminated to a 50 Ω load to absorb the
applied RF signals.
On mode. A low insertion loss path from the RFC
port to the RF2 port.
0 1
On mode. A low insertion loss path from the RFC port to
the RF1 port.
Off mode. The RF2 port is isolated from the RFC port
and is internally terminated to a 50 Ω load to absorb
the applied RF signals.
1 X
1
All in off mode. Both the RF1 and RF2 ports are isolated from the RFC port, and the RFC port is reflective.
1
X stands for don’t care.
HMC8038 Data Sheet
Rev. A | Page 10 of 11
APPLICATIONS INFORMATION
Generate the evaluation PCB used in the application shown in
Figure 17 with proper RF circuit design techniques. Signal lines
at the RF port must have a 50 Ω impedance, and the package
ground leads and backside ground slug must connect directly to
the ground plane, as shown in Figure 18. The evaluation board
shown in Figure 18 is available from Analog Devices, Inc. upon
request.
Table 8. Bill of Materials for Evaluation Board
EV1HMC8038LP4C
1
Reference Designator Description
J1 to J3 PCB mount SMA connector
C1 to C6 100 pF capacitor, 0402 package
C7 0.1 μF capacitor, 0402 package
R1, R2 0 Ω resistor, 0402 package
U1 HMC8038 SPDT switch
PCB
2
600-01267-00 evaluation PCB
1
Reference to this evaluation board number when ordering the complete
evaluation board.
2
Circuit board material: Roger 4350 or Arlon 25FR.
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
50
50
RF2
RF1
GND
GND
PACKAGE
BASE
C3
100pF
RFC
EN
V
CTL
V
DD
C1
100pF
C2
100pF
C6
100pF
C4
100pF
C7
0.1µF
C5
100pF
13554-017
Figure 17. HMC8038 Application Circuit
13554-018
Figure 18. EV1HMC8038LP4C Evaluation Board
Data Sheet HMC8038
Rev. A | Page 11 of 11
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.39
0.33
0.27
2.55
2.40 SQ
2.25
1
0.65
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
EXPOSED
PAD
PIN 1
INDIC
A
T
OR
(0.30)
0.70
0.60
0.50
SEA
TING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
1.00
0.90
0.80
COMPLIANT
TO
JEDEC STANDARDS MO-220-VGGC
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
08-14-2015-
A
PKG-000000
1.95 REF
Figure 19. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.90 mm Package Height
(CP-16-40)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range MSL Rating
2
Package Description Package Option Branding
3
HMC8038LP4CE 40°C to +105°C MSL3 16-lead Lead Frame Chip Scale Package [LFCSP] CP-16-40
XXXX
8038
HMC8038LP4CETR 40°C to +105°C MSL3 16-lead Lead Frame Chip Scale Package [LFCSP] CP-16-40
XXXX
8038
EV1HMC8038LP4C 40°C to +105°C Evaluation Board
1
RoHs-Compliant Part.
2
The maximum peak reflow temperature is 260°C.
3
4-digit lot number: XXXX.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13554-0-11/15(A)

HMC8038LP4CETR

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RF Switch ICs High isolation, non-reflective, single s
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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