NLV74HC32ADTR2G

© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 12
1 Publication Order Number:
MC74HC32A/D
MC74HC32A
Quad 2-Input OR Gate
High−Performance Silicon−Gate CMOS
The MC74HC32A is identical in pinout to the LS32. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7 A Requirements
Chip Complexity: 48 FETs or 12 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
3
Y1
1
A1
PIN 14 = V
CC
PIN 7 = GND
LOGIC DIAGRAM
2
B1
6
Y2
4
A2
5
B2
8
Y3
9
A3
10
B3
11
Y4
12
A4
13
B4
Y = A+B
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MARKING DIAGRAMS
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
TSSOP−14
DT SUFFIX
CASE 948G
SOIC−14 NB
D SUFFIX
CASE 751A
HC32AG
AWLYWW
1
14
HC
32A
ALYWG
G
1
14
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
TSSOP−14SOIC−14 NB
PIN ASSIGNMENT
1314 12 11 10 9 8
21 34567
V
CC
B4 A4 Y4 B3 A3 Y3
A1 B1 Y1 A2 B2 Y2 GND
14−Lead (Top View)
L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs Output
AB
L
H
H
H
Y
MC74HC32A
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2
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
V
in
DC Input Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±50 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature –65 to +150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
260
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types –55 +125
_C
t
r
, t
f
Input Rise and Fall Time V
CC
= 2.0 V
(Figure 1) V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
1000
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74HC32A
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3
DC CHARACTERISTICS (Voltages Referenced to GND)
V
CC
V
Guaranteed Limit
Symbol Parameter Condition −55 to 25°C 85°C 125°C Unit
V
IH
Minimum High−Level Input Voltage V
out
= 0.1V or V
CC
−0.1V
|I
out
| 20mA
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
V
IL
Maximum Low−Level Input Voltage V
out
= 0.1V or V
CC
− 0.1V
|I
out
| 20mA
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| 20mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
=V
IH
or V
IL
|I
out
| 2.4mA
|I
out
| 4.0mA
|I
out
| 5.2mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| 20mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| 2.4mA
|I
out
| 4.0mA
|I
out
| 5.2mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
I
in
Maximum Input Leakage Current V
in
= V
CC
or GND 6.0 ±0.1 ±1.0 ±1.0
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0mA
6.0 1.0 10 40
mA
AC CHARACTERISTICS (C
L
= 50pF, Input t
r
= t
f
= 6ns)
V
CC
V
Guaranteed Limit
Symbol Parameter −55 to 25°C 85°C 125°C Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
C
in
Maximum Input Capacitance 10 10 10 pF
C
PD
Power Dissipation Capacitance (Per Buffer)*
Typical @ 25°C, V
CC
= 5.0 V, V
EE
= 0 V
pF
20
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
.

NLV74HC32ADTR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Logic Gates QUAD OR GATE
Lifecycle:
New from this manufacturer.
Delivery:
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