10
2321H–CNFG–03/06
AT17LV65/128/256/512/010/002/040
7. Cascading Serial Configuration EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration
memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator asserts its
CEO
output Low and disables its DATA line driver. The second configurator recognizes the Low
level on its CE
input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are reset if
the RESET
/OE on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET
/OE input can be
tied to its inactive (High) level.
The AT17LV65 devices do not have the CEO
feature to perform cascaded configurations.
8. AT17LV Series Reset Polarity
The AT17LV series configurator allows the user to program the reset polarity as either
RESET/OE
or RESET/OE. This feature is supported by industry-standard programmer
algorithms.
9. Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be pro-
grammed by the Two-Wire serial bus. The programming is done at V
CC
supply only.
Programming super voltages are generated inside the chip.
10. Standby Mode
The AT17LV series configurators enter a low-power standby mode whenever CE is asserted
High. In this mode, the AT17LV65/128/256 configurator consumes less than 50 µA of current at
3.3V (100 µA for the AT17LV512/010 and 200 µA for the AT17LV002/040). The output remains
in a high-impedance state regardless of the state of the OE
input.
